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Prasenjit B Biswas

from Cupertino, CA
Age ~72
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Also known as:
Biswas Prasenjit, T Biswas
Phone and address:
22219 Hammond Way, Cupertino, CA 95014
(408) 253-3727
Related to:
Jefferson Andrea Bennett, 39Sherri Aliene Mackey, 55Konina Biswas, 37Konina Biswas, 35Sanjit Biswas, 43Mitali Biswas, 72Hope H Biswas, 43Richard E Hamrick, 75
Connected to:
Anukul Biswas, 41Barnali Biswas, 42Bijoy Biswas, 40Bina Biswas, 50Biswajit Biswas, 62Dave M Biswas, 45Debarshi Biswas, 40Debkumar Biswas, 36Dipayan Biswas, 51Dipshikha Biswas, 50

Prasenjit Biswas Phones & Addresses

  • 22219 Hammond Way, Cupertino, CA 95014 (408) 253-3727
  • 20167 Pampas Ct, Saratoga, CA 95070
  • 109 Kingsbridge Dr, Garland, TX 75040
  • Sunnyvale, CA
  • San Jose, CA

Work

Company: Presto Nov 2014 Position: Solution architect

Education

School / High School: 1. The Institute of Computer Studies- Mississauga, ON 1998

Resumes

Resumes

Prasenjit Biswas Photo 1

Independent Technology Strategy Consultant

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Mips Jan 2014 - Mar 2015
Senior Technician Strategy Consultant
Independent Tech Strategy Jan 2014 - Mar 2015
Independent Technology Strategy Consultant
Arm Jul 2012 - Sep 2013
Senior Principal Engineer and Data Center Architect
Intel Corporation Mar 2004 - Jun 2012
Senior Manager Micro Architecture Validation, Technical Lead, Senior Staff Silicon Architect
Cortina Systems Jan 2002 - Mar 2004
Director of Engineering
Education:
University of Alberta 1981 - 1983
Master of Science, Masters, Computer Engineering Jadavpur University
Bachelor of Engineering, Bachelors, Electronics, Engineering, Communications
Skills:
Asic
Processors
Multi Core
Embedded Systems
Semiconductors
Microprocessors
Product Management
Firmware
Digital Signal Processors
Program Management
Arm
Distributed Systems
System Architecture
Simulations
Debugging
Soc
Low Power Design
Algorithms
Computer Architecture
Microarchitecture
Intel
Functional Verification
International Development
Director of Engineering/ Senior Engineering Manager
Performance Analysis
Rtl Design
Ic
Verilog
Microarch Validation
Instruction Set Design
Engineering Management
Management
Architecture
Micro Servers
Cloud Computing
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Prasenjit Biswas

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Prasenjit Biswas

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Prasenjit Biswas

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Prasenjit Biswas

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Prasenjit Biswas Mississauga, ON

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Work:
PRESTO

Nov 2014 to Dec 2014
Solution Architect
ADP

Sep 2014 to Nov 2014
Solution Architect
Shoppers Drug Mart

Jan 2014 to Jun 2014
Program Architect
DirecTV
Los Angeles, CA
Feb 2013 to Oct 2013
Enterprise Solution Architect
TD Insurance

Apr 2011 to Jan 2013
Solution Architect
Manulife Financial

Mar 2009 to Dec 2010
Solution Architect
First Canadian Title

Nov 2007 to Jan 2009
Solution Architect
Adea Solutions

Jun 2007 to Dec 2007
ETL Developer (freelance)
Adea Solutions
Dallas, TX
Mar 2007 to Dec 2007
Integration Architect
Cactus Commerce

May 2006 to Mar 2007
Integration Analyst
ING DIRECT (USA)

May 2005 to May 2006
Lead Developer/Analyst
BizTalk

2006 to 2006
Enterprise Data Warehouse
Bell, ON
Jan 2004 to Mar 2005
Team Lead and Architect
Centre for Advanced Visualization

Aug 2003 to Nov 2003
GIS, Object Oriented Development
Percepsys Inc

Jan 2003 to Jul 2003
Technical Architect / Developer
Centre for Advanced Visualization

1996 to 2003
Architect / Developer
Economical Insurance

May 2002 to Nov 2002
Technical Architect
Detroit
Toronto, ON
Mar 2001 to Apr 2002
Team Lead
Winnipeg

Jan 2001 to Mar 2001
Technical Team Lead
Navantis
Toronto, ON
Jul 2000 to Dec 2000
Web Applications Developer
NexInnovations
Toronto, ON
Mar 2000 to Jul 2000
Web Applications Developer
DSPA Software
Toronto, ON
Aug 1999 to Feb 2000
Web Applications Developer
GMASCO
Toronto, ON
Feb 1999 to Jul 1999
Web Content Developer
Centre for Advanced Visualization
Dubai
Jan 1996 to Mar 1998
HTML, Home Site, Macintosh, Illustrator

Business Records

Name / Title
Company / Classification
Phones & Addresses
Prasenjit Biswas
President
SARATOGA PARK ASSOCIATION
12135 Plumas Dr, Saratoga, CA 95070

Publications

Wikipedia References

Prasenjit Biswas Photo 7

Prasenjit Biswas

Education:
Studied at:

Assam University

Academic degree:

Philosophiae Doctor

Skills & Activities:
Master status:

Indigenous

Prasenjit Biswas Photo 8

Prasenjit Biswas

Us Patents

Floating Point Unit Pipeline Synchronized With Processor Pipeline

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US Patent:
6418528, Jul 9, 2002
Filed:
Aug 10, 1998
Appl. No.:
09/131881
Inventors:
Prasenjit Biswas - Saratoga CA
Gautam Dewan - Cupertino CA
Kevin Iadonato - San Jose CA
Norio Nakagawa - Tokyo, JP
Kunio Uchiyama - Tokyo, JP
Assignee:
Hitachi America, Ltd. - Brisbane CA
International Classification:
G06F 9302
US Classification:
712212
Abstract:
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Floating Point Unit Pipeline Synchronized With Processor Pipeline

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US Patent:
6772327, Aug 3, 2004
Filed:
May 9, 2002
Appl. No.:
10/143230
Inventors:
Prasenjit Biswas - Saratoga CA
Gautam Dewan - Cupertino CA
Kevin Iadonato - San Jose CA
Norio Nakagawa - Tokyo, JP
Kunio Uchiyama - Tokyo, JP
Assignee:
Hitachi Micro Systems, Inc. - San Jose CA
International Classification:
G06F 938
US Classification:
712245, 712220, 712221, 712222, 712244
Abstract:
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Floating Point Unit Pipeline Synchronized With Processor Pipeline

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US Patent:
7162616, Jan 9, 2007
Filed:
Mar 8, 2004
Appl. No.:
10/796552
Inventors:
Prasenjit Biswas - Saratoga CA, US
Gautam Dewan - Cupertino CA, US
Kevin Iadonato - San Jose CA, US
Norio Nakagawa - Tokyo, JP
Kunio Uchiyama - Tokyo, JP
Assignee:
Renesas Technology America, Inc. - San Jose CA
International Classification:
G06F 9/312
US Classification:
712225, 712218
Abstract:
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

Modeling A Mixed-Language Mixed-Signal Design

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US Patent:
7260792, Aug 21, 2007
Filed:
May 10, 2005
Appl. No.:
11/126497
Inventors:
Chandrashekar L. Chetput - Santa Clara CA, US
Ramesh S. Mayiladuthurai - San Jose CA, US
Prasenjit Biswas - Sunnyvale CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 2, 716 4
Abstract:
A method for modeling a mixed-language and mixed-signal (MLMS) design is disclosed. The method includes receiving an MLMS design comprising at least a digital driver, a digital receiver, and an analog block connected by an MLMS net in a hierarchical structure and identifying analog-digital boundaries of the MLMS design. For each analog-digital boundary, the method further includes a) selecting a connect module (CM) by using a predetermined discipline resolution procedure; b) determining input driving values of the CM; and c) connecting the digital driver, the digital receiver, and the analog block to the CM. The method repeats steps a), b), and c) on all analog-digital boundaries of the MLMS design.

Flexible Macroblock Ordering And Arbitrary Slice Ordering Apparatus, System, And Method

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US Patent:
8126046, Feb 28, 2012
Filed:
Jun 30, 2006
Appl. No.:
11/479324
Inventors:
Yi-Jen Chiu - San Jose CA, US
Prasenjit Biswas - Saratoga CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 7/12
H04B 1/66
US Classification:
37524001, 3484251
Abstract:
A system, apparatus, method, and article to process a flexible macroblock ordering and arbitrary slice ordering are described. The apparatus may include a video decoder. The video decoder includes a processor to store coding parameters of one or more neighboring macroblocks in a data buffer. The neighboring macroblocks are previously decoded macroblocks and are adjacent to a current macroblock. The processor is to store control parameters for each of the one or more neighboring macroblocks in the data buffer. The processor is to reconstruct coding parameters for the current macroblock using availability information associated with the neighboring macroblocks.

Chroma Motion Vector Processing Apparatus, System, And Method

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US Patent:
8379723, Feb 19, 2013
Filed:
Jun 27, 2006
Appl. No.:
11/475413
Inventors:
Yi-Jen Chiu - San Jose CA, US
Mei-Chen Yeh - Goleta CA, US
Prasenjit Biswas - Saratoga CA, US
Louis Lippincott - Los Altos CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 7/12
US Classification:
37524016
Abstract:
A system, apparatus, method, and article to process a chroma motion vector are described. The apparatus may include a video decoder. The video decoder includes a processor to receive a compressed video bitstream. The compressed video bitstream includes a stream of pictures. The stream of pictures includes a current slice and a current block within the slice. The processor pre-computes a chroma motion vector adjustment parameter for the current slice and determines a motion vector component for the current block within the current slice using the pre-computed chroma motion vector adjustment parameter.

Hardware Accelerated Compressed Video Bitstream Escape Code Handling

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US Patent:
8630354, Jan 14, 2014
Filed:
Jun 16, 2006
Appl. No.:
11/454410
Inventors:
Musa Jahanghir - Palo Alto CA, US
Adrian R. Pearson - Phoenix AZ, US
Prasenjit Biswas - Saratoga CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04N 7/12
US Classification:
37524026, 37524001
Abstract:
Apparatus, systems and methods for hardware accelerated compressed video bitstream escape code handling are disclosed including an apparatus comprising a bitstream parser (BSP) to parse a bitstream of compressed video data. The BSP includes circuitry to extract uncompressed run and level data from the bitstream when the BSP detects an escape code in the bitstream. Other implementations are disclosed.

Flexible Macroblock Ordering And Arbitrary Slice Ordering Apparatus, System, And Method

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US Patent:
8644392, Feb 4, 2014
Filed:
Feb 7, 2012
Appl. No.:
13/367449
Inventors:
Yi-Jen Chiu - San Jose CA, US
Prasenjit Biswas - Saratoga CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04B 1/66
H04N 7/12
US Classification:
37524016, 3484261
Abstract:
A system, apparatus, method, and article to process a flexible macroblock ordering and arbitrary slice ordering are described. The apparatus may include a video decoder. The video decoder includes a processor to store coding parameters of one or more neighboring macroblocks in a data buffer. The neighboring macroblocks are previously decoded macroblocks and are adjacent to a current macroblock. The processor is to store control parameters for each of the one or more neighboring macroblocks in the data buffer. The processor is to reconstruct coding parameters for the current macroblock using availability information associated with the neighboring macroblocks.

Isbn (Books And Publications)

Political Economy of Underdevelopment of North-East India

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Author

Prasenjit Biswas

ISBN #

8187606398

Peace in India's North-East: Meaning, Metaphor, and Method Essays of Concern and Commitment

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Author

Prasenjit Biswas

ISBN #

8189233483

Control profile
Prasenjit B Biswas from Cupertino, CA, age ~72 Get Report