Lawrence Cy Wei Hung

6429682, Aug 6, 2002

May 25, 2001

09/865813

David P. Schultz - San Jose CA
Lawrence C. Hung - San Jose CA
F. Erich Goetting - Cupertino CA

Xilinx, Inc. - San Jose CA

H03K 19173

326 41, 326 38, 326 39

A bus interface circuit for a programmable logic device (PLD) including an interface multiplexer connected between two or more external communication circuits and a configuration memory array. The interface multiplexer coordinates communication between a selected one of the external communication circuits and a packet processor. The packet processor interprets command/data information transmitted in a bit stream from the selected external communication circuit. In a default state, the interface multiplexer connects dual-purpose input/output pins of the PLD to the packet processor. In an alternative state, the interface multiplexer connects a JTAG interface circuit to the packet processor to facilitate configuration operations through the JTAG pins of the PLD.

6429715, Aug 6, 2002

Jan 13, 2000

09/482741

Shekhar Bapat - San Jose CA
Lawrence C. Hung - San Jose CA

Xilinx, Inc. - San Jose CA

G06F 104

327295, 327565, 327158

An integrated circuit receives an external clock signal and generates therefrom a clock signal that is supplied to a plurality of external devices. A delay-locked loop (DLL), a balanced clock tree, and a plurality of interface cells on the integrated circuit function together to supply the clock signal to the plurality of external devices such that the clock signal at each of the external devices is deskewed with respect to the external clock signal. Board level design is simplified because no balanced clock tree is needed to route the clock signal from the integrated circuit to the external devices, rather each external device is coupled to a corresponding one of the interface cells via a separate external connection. Each of these external connections has an equal propagation delay. One of the interface cells supplies the clock signal back to a reference signal input of the DLL via an external connection.

6507211, Jan 14, 2003

Jul 29, 1999

09/363990

David P. Schultz - San Jose CA
Lawrence C. Hung - San Jose CA
F. Erich Goetting - Cupertino CA

Xilinx, Inc. - San Jose CA

G06F 738

326 37, 326 38, 326 39

A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBs) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that-results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The user data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.

6525562, Feb 25, 2003

Apr 30, 2002

10/136141

David P. Schultz - San Jose CA
Lawrence C. Hung - San Jose CA
F. Erich Goetting - Cupertino CA

Xilinx, Inc. - San Jose CA

H03K 19177

326 39, 326 41

A programmable logic device (PLD) can be reconfigured without losing state data derived from logical operations performed using a previous logic configuration. One PLD in accordance with the invention includes a number of configurable logic blocks (CLBS) and input/output blocks (IOBs). Each CLB and IOB includes a number of configuration memory cells adapted to store the logical function of the FPGA. Each CLB and IOB additionally includes user storage elements adapted to store state data that results from the PLD performing a programmed logical function, such as a selected combinatorial function of input signals. The PLD preserves the data stored in the user storage element as the PLD is reconfigured. The state data is therefore available for use by the PLD after the PLD is reconfigured to perform a new logic function.

61916145, Feb 20, 2001

Aug 13, 1999

9/374466

David P. Schultz - San Jose CA
Lawrence C. Hung - San Jose CA
F. Erich Goetting - Cupertino CA

Xilinx, Inc. - San Jose CA

H03K 19177

326 41

A cyclic redundancy check (CRC) register is connected to the bi-directional bus and a packet processor in a configuration circuit of an FPGA. The CRC register performs transmission error detection functions based on the command/data transmissions to various registers connected to the bus, and based on the address information transmitted from the packet processor to an address/operand decoder used to enable the various registers to receive subsequent command/data words. The CRC register calculates a check-sum value in accordance with a predetermined equation. At any time during the transmission (e. g. , halfway through configuration or at the end of configuration), a pre-calculated check-sum value is transmitted to the CRC register that represents an expected check-sum value at the selected time. The pre-calculated check-sum value is then compared with the check-sum value currently stored in the CRC register. If the pre-calculated check-sum value does not equal the current check-sum value, then an error signal is generated that notifies a user that a transmission error has occurred.

58381678, Nov 17, 1998

May 13, 1997

8/855029

Charles R. Erickson - Fremont CA
Lawrence Cy-Wei Hung - Los Gatos CA

Xilinx, Inc. - San Jose CA

H03K 19177

326 38

An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.

54306876, Jul 4, 1995

Apr 1, 1994

8/223247

Lawrence C. Hung - Los Gatos CA
Charles R. Erickson - Fremont CA

Xilinx, Inc. - San Jose CA

G11C 1300

36523008

A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells.

56401060, Jun 17, 1997

May 26, 1995

8/451781

Charles R. Erickson - Fremont CA
Lawrence Cy-Wei Hung - Los Gatos CA

Xilinx, Inc. - San Jose CA

H03K 19177

326 38

An apparatus and method for decreasing the amount of time necessary to load configuration data into Field Programmable Gate Arrays (FPGAs) or other integrated circuit devices. In a preferred embodiment, serially arrayed FPGAs receive a concatenated stream of data from a common data bus. As a first FPGA reaches a loading-complete state, an enabling token is passed from the first FPGA to an enabling input on the next FPGA. The process repeats until all devices are completely loaded or fully configured.