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Siu M Chan

from Elk Grove, CA
Age ~88
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Also known as:
Siu Ming Chan, Siu Mildred Chan, Steve Ming Chan, Steve M Chan, Ming Chan Siu, Siu Ming Chang, Scott Chan, Stephen Chan, Siu Mchan
Phone and address:
3016 W Sondiesa Ct, Elk Grove, CA 95758
Related to:
Chang Tao, 77
Connected to:
Ain N Chan, 75Anny Chan, 59Art Chan, 69Ath S Chan, 59Beckie Chan, 44Bopha Chan, 57Bor Y Chan, 62Brain H Chan, 45Bun Chan, 44Carin B Chan, 61

Siu Chan Phones & Addresses

  • 3016 W Sondiesa Ct, Elk Grove, CA 95758
  • Albany, CA
  • San Leandro, CA
  • Pacifica, CA
  • Sacramento, CA
  • Alameda, CA
  • Concord, CA

Professional Records

Medicine Doctors

Siu Chan Photo 1

Dr. Siu W Chan, San Francisco CA - MD (Doctor of Medicine)

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Specialties:
Diagnostic Radiology
Roentgenology
Address:
2323 Noriega St Suite 208, San Francisco, CA 94122
(415) 759-7888 (Phone), (415) 759-7890 (Fax)
Certifications:
Diagnostic Roentgenology
Awards:
Healthgrades Honor Roll
Languages:
English
Education:
Medical School
National Chung Shan University (Sun Yat Sen) Medical College
Medical School
St Elizabeth Hosp
Medical School
Grad Hosp U Penn
Siu Chan Photo 2

Siu Fung Chan

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Specialties:
Anesthesiology
Work:
University Of Cincinnati Physicians Anesthesiology
234 Goodman St, Cincinnati, OH 45219
(513) 558-4194 (phone), (513) 558-0995 (fax)
Education:
Medical School
University of Cincinnati College of Medicine
Graduated: 2009
Languages:
English
Description:
Dr. Chan graduated from the University of Cincinnati College of Medicine in 2009. He works in Cincinnati, OH and specializes in Anesthesiology. Dr. Chan is affiliated with UC Medical Center.
Siu Chan Photo 3

Siu Fung Chan

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Specialties:
Anesthesiology
Pain Medicine
Education:
University of Cincinnati *
Siu Chan Photo 4

Siu Wan Chan, San Francisco CA

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Specialties:
Dentist
Address:
2323 Noriega St, San Francisco, CA 94122

Lawyers & Attorneys

Siu Chan Photo 5

Siu Chan - Lawyer

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ISLN:
1000711822
Admitted:
2013
Siu Chan Photo 6

Siu Chan - Lawyer

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Office:
Lo, Wong & Tsui
ISLN:
919756425
Admitted:
1977

Business Records

Name / Title
Company / Classification
Phones & Addresses
Siu Tau Chan
Owner
Ideal Productions
Radio and Television Broadcasting and Communi...
2525 Van Ness, San Francisco, CA 94109
Siu Tau Chan
Owner
Ideal Productions
Radio and Television Broadcasting and Communi...
2525 Van Ness, San Francisco, CA 94109
Siu L. Chan
President
MARCO FASHION INC
1032 Stockton St, San Francisco, CA 94108
Siu Hung Chan
President
SPEEDY BBQ, INC
39055 Cedar Blvd STE 186, Newark, CA 94560
Siu Hung Chan
President
CHAN'S GARDEN, INC
1780 Clear Lk Ave STE 236, Milpitas, CA 95035
Siu Chan
Owner
Chans Restaurant
Eating Place
3116 Stockton Blvd, Sacramento, CA 95820
(916) 731-7020
Siu P. Chan
Principal
Hong Kong Restaurant
Eating Place
46831 Warm Spg Blvd, Fremont, CA 94539
Siu W. Chan
Family And General Dentistry
Chan Siu Wan DDS
Dentist's Office
2415 Noriega St, San Francisco, CA 94122
Siu Wan Chan
San Bruno Avenue Properties LLC
Real Estate Development · Dental Clinic · Professional/Dental Practice Consulting,
2323 Noriega St, San Francisco, CA 94122
2817 San Bruno Ave, San Francisco, CA 94134

Publications

Us Patents

Non-Volatile Memory And Method With Control Gate Compensation For Source Line Bias Errors

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US Patent:
7170784, Jan 30, 2007
Filed:
Apr 1, 2005
Appl. No.:
11/097502
Inventors:
Siu Lung Chan - San Jose CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 11/34
G11C 16/06
US Classification:
36518512, 36518503, 36518521
Abstract:
Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.

Non-Volatile Memory And Method With Compensation For Source Line Bias Errors

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US Patent:
7173854, Feb 6, 2007
Filed:
Apr 1, 2005
Appl. No.:
11/097038
Inventors:
Siu Lung Chan - San Jose CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 11/34
G11C 16/04
G11C 16/24
G11C 16/26
US Classification:
36518512, 3651852, 3652385, 36518909, 36518503
Abstract:
Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate and drain voltages. This error is minimized when the applied control gate and drain voltages have their reference point located as close as possible to the sources of the memory cells. In one preferred embodiment, the reference point is located at a node where the source control signal is applied. When a memory array is organized in pages of memory cells that are sensed in parallel, with the sources in each page coupled to a page source line, the reference point is selected to be at the page source line of a selected page via a multiplexor.

Apparatus For Controlled Programming Of Non-Volatile Memory Exhibiting Bit Line Coupling

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US Patent:
7206235, Apr 17, 2007
Filed:
Oct 14, 2005
Appl. No.:
11/251458
Inventors:
Jeffrey W. Lutze - San Jose CA, US
Yan Li - Milpitas CA, US
Siu L. Chan - San Jose CA, US
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
G11C 7/00
US Classification:
365195, 36518502, 36518517, 36518518, 36518524
Abstract:
The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

Methods For Improved Program-Verify Operations In Non-Volatile Memories

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US Patent:
7224614, May 29, 2007
Filed:
Dec 29, 2005
Appl. No.:
11/323596
Inventors:
Siu Lung Chan - San Jose CA, US
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
G11C 16/06
US Classification:
36518522, 36518518, 36518519, 3651852, 36518524, 36518503
Abstract:
In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

Non-Volatile Memory And Method With Power-Saving Read And Program-Verify Operations

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US Patent:
7251160, Jul 31, 2007
Filed:
Mar 16, 2005
Appl. No.:
11/083514
Inventors:
Yan Li - Milpitas CA, US
Seungpil Lee - San Ramon CA, US
Siu Lung Chan - San Jose CA, US
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
G11C 11/34
US Classification:
36518503, 36518522, 36518524
Abstract:
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

Method For Controlled Programming Of Non-Volatile Memory Exhibiting Bit Line Coupling

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US Patent:
7286406, Oct 23, 2007
Filed:
Oct 14, 2005
Appl. No.:
11/250735
Inventors:
Jeffrey W. Lutze - San Jose CA, US
Yan Li - Milpitas CA, US
Siu L. Chan - San Jose CA, US
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
G11C 16/04
US Classification:
36518518, 36518517, 36518523
Abstract:
The effects of bit line-to-bit line coupling in a non-volatile memory are addressed. An inhibit voltage is applied on a bit line of a storage element to be programmed to inhibit programming during a portion of a program voltage. The inhibit voltage is subsequently removed during the program voltage to allow programming to occur. Due to the proximity of bit lines, the change in the bit line voltage is coupled to a neighboring unselected bit line, reducing the neighboring bit line voltage to a level which might be sufficient to open a select gate and discharge a boost voltage. To prevent this, the select gate voltage is temporarily adjusted during the change in the bit line voltage to ensure that the biasing of the select gate on the unselected bit line is not sufficient to open the select gate.

Non-Volatile Memory With Improved Program-Verify Operations

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US Patent:
7310255, Dec 18, 2007
Filed:
Dec 29, 2005
Appl. No.:
11/323577
Inventors:
Siu Lung Chan - San Jose CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 11/34
US Classification:
365 22, 36518503, 36518524
Abstract:
In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

Method For Compensated Sensing In Non-Volatile Memory

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US Patent:
7324393, Jan 29, 2008
Filed:
Dec 28, 2005
Appl. No.:
11/321681
Inventors:
Siu Lung Chan - San Jose CA, US
Assignee:
Sandisk Corporation - Milpitas CA
International Classification:
G11C 7/00
US Classification:
365205, 365207, 36518901, 36518907, 36518521
Abstract:
One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.
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Siu M Chan from Elk Grove, CA, age ~88 Get Report