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Sherman H Yip

from Sunnyvale, CA
Age ~47
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Also known as:
Sherman Hang Cheuk Yip, Yip Sherman
Phone and address:
693 E Mc Kinley Ave, Sunnyvale, CA 94086
Related to:
Yiu Hong Yip, 72Hong Yip Yiu, 48Jacky Yip, 50Rocky Yip, 41
Connected to:
Alvin Yip, 32Bobbie Yip, 65Deanna W Yip, 32Diana Yip, 62Douglas K Yip, 67Elizabeth L Yip, 79Eva Yip, 39Frankie Yip, 30Gregory Yip, 49Jane Yip, 64

Sherman Yip Phones & Addresses

  • 693 E Mc Kinley Ave, Sunnyvale, CA 94086
  • 140 Orsi Cir, San Francisco, CA 94124 (415) 297-8025
  • Davis, CA
  • Santa Clara, CA

Resumes

Resumes

Sherman Yip Photo 1

Project Engineer

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Location:
1100 Ocean Ave, San Francisco, CA 94112
Work:
Walters & Wolf
Project Engineer
Education:
Uc San Diego 2014 - 2019
Bachelors, Bachelor of Science
Sherman Yip Photo 2

Senior Principal Engineer

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Location:
693 east Mc Kinley Ave, Sunnyvale, CA 94086
Industry:
Computer Hardware
Work:
Startup
Senior Principal Engineer
Oracle
Senior Manager
Sun Microsystems Jun 2000 - Jun 2011
Staff Engineer
Education:
University of California, Davis 2000 - 2000
Bachelors, Bachelor of Science, Computer Science University of California
Skills:
Debugging
Perl
Microprocessors
Solaris
System Architecture
Computer Architecture
Processors
Sparc
Sun
Sherman Yip Photo 3

Sherman Yip

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Sherman Yip Photo 4

Staff Engineer At Sun Microsystems

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Position:
Staff Engineer at Sun Microsystems
Location:
San Francisco Bay Area
Industry:
Computer Hardware
Work:
Sun Microsystems since Jun 2000
Staff Engineer
Education:
University of California, Davis 2000
BS, Computer Science

Publications

Us Patents

Method And Apparatus For Dynamically Adjusting The Aggressiveness Of An Execute-Ahead Processor To Hide Memory Latency

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US Patent:
7293163, Nov 6, 2007
Filed:
Mar 22, 2004
Appl. No.:
10/807093
Inventors:
Paul Caprioli - Mountain View CA, US
Sherman H. Yip - San Francisco CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 9/30
G06F 9/40
G06F 15/00
US Classification:
712218, 712214, 712216, 712219
Abstract:
One embodiment of the present invention provides a system that dynamically adjusts the aggressiveness of an execute-ahead processor. If a data-dependent stall condition is encountered during program execution, the system enters an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and other non-deferred instructions are executed in program order. If a non-data-dependent stall condition is encountered during execute-ahead mode, the system enters a scout mode, wherein instructions are speculatively executed to prefetch future loads, but results are not committed to the architectural state of the execute-ahead processor. On the other hand, if an unresolved data dependency is resolved during the execute-ahead mode, enters a deferred mode and executes deferred instructions. During this deferred mode, if some instructions are deferred again, the system determines whether to resume execution in the execute-ahead mode. If it determines to do so, the system resumes execution in the execute-ahead mode, and otherwise resumes execution in a non-aggressive mode.

Method For Graphically Displaying Hardware Performance Simulators

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US Patent:
7331039, Feb 12, 2008
Filed:
Oct 15, 2003
Appl. No.:
10/688763
Inventors:
Sherman H. Yip - San Francisco CA, US
Paul Caprioli - Mountain View CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 9/44
G06F 3/048
US Classification:
717125, 717128, 717135, 715772, 715967
Abstract:
A method for graphically tracking progression of instructions through hardware components. Instructions of a code segment are defined by graphical icons where each graphical icon has a displayable appearance that identifies a type of instruction. The method tracks each graphical icon when simulating execution of the code segment through the hardware components. The method then displays a progression of each graphical icon through the hardware components during execution of the code segment.

Method And Apparatus For Sampling Instructions On A Processor That Supports Speculative Execution

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US Patent:
7418581, Aug 26, 2008
Filed:
Apr 17, 2006
Appl. No.:
11/405965
Inventors:
Shailender Chaudhry - San Francisco CA, US
Paul Caprioli - Mountain View CA, US
Sherman H. Yip - San Francisco CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 9/30
US Classification:
712227
Abstract:
One embodiment of the present invention provides a system that samples instructions on a processor that supports speculative-execution. The system starts by selecting an instruction, wherein selecting an instruction involves selecting an instruction that is received from an instruction fetch unit or a deferred queue, wherein the deferred queue holds deferred instructions which are deferred because of an unresolved data dependency. The system then records information about the selected instruction during execution of the selected instruction, whereby the recorded information can be used to determine the performance of the processor.

Circuitry And Method For Accessing An Associative Cache With Parallel Determination Of Data And Data Availability

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US Patent:
7461208, Dec 2, 2008
Filed:
Jun 16, 2005
Appl. No.:
11/155147
Inventors:
Paul Caprioli - Mountain View CA, US
Sherman H. Yip - San Francisco CA, US
Shailender Chaudhry - San Francisco CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 13/16
US Classification:
711128
Abstract:
A circuit for accessing an associative cache is provided. The circuit includes data selection circuitry and an outcome parallel processing circuit both in communication with the associative cache. The outcome parallel processing circuit is configured to determine whether an accessing of data from the associative cache is one of a cache hit, a cache miss, or a cache mispredict. The circuit further includes a memory in communication with the data selection circuitry and the outcome parallel processing circuit. The memory is configured to store a bank select table, whereby the bank select table is configured to include entries that define a selection of one of a plurality of banks of the associative cache from which to output data. Methods for accessing the associative cache are also described.

Method And Structure For Pipelining Of Simd Conditional Moves

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US Patent:
7480787, Jan 20, 2009
Filed:
Jan 27, 2006
Appl. No.:
11/341001
Inventors:
Paul Caprioli - Mountain View CA, US
Lawrence A. Spracklen - Boulder Creek CA, US
Sherman H. Yip - San Francisco CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 9/00
US Classification:
712224, 712 5
Abstract:
A mask is first generated in a general-purpose integer register. The mask is generated by executing a single instruction multiple data (SIMD) instruction on a plurality of operands stored in a plurality of registers and by writing the result to the general-purpose integer register. Next, a conditional-move mask is generated in a register using the mask, and then the conditional-move mask is used in selecting operands from the plurality of operands to generate a result in another register.

Mechanism For Hardware Tracking Of Return Address After Tail Call Elimination Of Return-Type Instruction

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US Patent:
7610474, Oct 27, 2009
Filed:
Feb 10, 2006
Appl. No.:
11/352147
Inventors:
Paul Caprioli - Mountain View CA, US
Sherman H. Yip - San Francisco CA, US
Shailender Chaudhry - San Francisco CA, US
Assignee:
Sun Microsystems, Inc. - Menlo Park CA
International Classification:
G06F 9/00
US Classification:
712239
Abstract:
A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one embodiment of the invention, an apparatus includes a processor pipeline and at least a first return address stack for maintaining a stack of return addresses associated with instruction flow at a first stage of the processor pipeline. The processor pipeline is configured to maintain the first return address stack unchanged in response to detection of a tail-call elimination sequence of one or more instructions associated with a first call-type instruction encountered by the first stage. The processor pipeline is configured to push a return address associated with the first call-type instruction onto the first return address stack otherwise.

Method And Apparatus For Reporting Failure Conditions During Transactional Execution

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US Patent:
7617421, Nov 10, 2009
Filed:
Jul 27, 2006
Appl. No.:
11/495452
Inventors:
Paul Caprioli - Santa Clara CA, US
Sherman H. Yip - San Francisco CA, US
Shailender Chaudhry - San Francisco CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 11/00
US Classification:
714 49, 714 16
Abstract:
One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution, and resumes normal non-transactional execution of the program past the block of instructions. Otherwise, if transactional execution of the block of instructions fails, the system discards changes made during the transactional execution, and records failure information indicating why the transactional execution failed.

Avoiding Live-Lock In A Processor That Supports Speculative Execution

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US Patent:
7634639, Dec 15, 2009
Filed:
Aug 23, 2005
Appl. No.:
11/210557
Inventors:
Shailender Chaudhry - San Francisco CA, US
Paul Caprioli - Mountain View CA, US
Sherman H. Yip - San Francisco CA, US
Guarav Garg - Sunnyvale CA, US
Ketaki Rao - San Francisco CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G06F 9/30
US Classification:
712225, 712219
Abstract:
One embodiment of the present invention provides a system which avoids a live-lock state in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during the execution of an instruction (a “launch instruction”) which causes the processor to enter a speculative-execution mode, the system checks status indicators associated with a forward progress buffer. If the status indicators indicate that the forward progress buffer contains data for the launch instruction, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators. The system then continues to issue instructions for execution in program order in normal-execution mode.
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Sherman H Yip from Sunnyvale, CA, age ~47 Get Report