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Satish S Soman

from Cupertino, CA
Age ~64
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Also known as:
Jyotsna S Soman, Satish Soman Satej, Jyotsna S Saman
Phone and address:
21663 Castleton St, Cupertino, CA 95014
Related to:
Rucha Soman
Connected to:
Aarati V Soman, 41Abhay B Soman, 97Anuradha K Soman, 52Joseph M Soman, 34Maitreyi G Soman, 37Maneesha Soman, 45Manu Soman, 44Narine P Soman, 67Neela R Soman, 67Rakesh Soman, 50

Satish Soman Phones & Addresses

  • 21663 Castleton St, Cupertino, CA 95014
  • 1541 Vista Club Cir, Santa Clara, CA 95054 (408) 564-6384
  • 8 John Pratt Cir, Westborough, MA 01581 (508) 366-5448
  • 9 John Pratt Cir, Westborough, MA 01581
  • Milford, MA
  • San Jose, CA
  • Shrewsbury, MA
  • Hudson, MA

Resumes

Resumes

Satish Soman Photo 1

Vice President Asic Design

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Location:
San Francisco, CA
Industry:
Telecommunications
Work:
Infinera
Vice President Asic Design
Axis Semiconductor Atrenta Meem Technologies Chromagic Mimansa Qtr Capital Management Aug 2015 - Aug 2017
Technical Advisor and Consultant
Appliedmicro Sep 2012 - Jun 2014
Fellow, Connectivity Division
Atrenta Jun 2005 - Aug 2012
Chief Solutions Architect
Axiowave Networks Jun 2002 - Jan 2005
Vice President Software, Chips and Architecture
Education:
Syracuse University Aug 1984 - May 1986
Master of Science, Masters, Vlsi Design, Computer Engineering Indian Institute of Technology, Bombay Aug 1977 - 1982
Skills:
Asic
Eda
Debugging
Application Specific Integrated Circuits
Architecture
C++
C
Cmos
Executive Management
Satish Soman Photo 2

Satish Soman

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Satish Soman
Vpresident Architecture And Chip Development
Axiowave
Business Consulting Services · Computer Repair
200 Nickerson Rd, Marlboro, MA 01752
100 Nickerson Rd, Marlborough, MA 01752
(508) 460-6969, (774) 348-4000

Publications

Us Patents

Mpeg Video Decoder Having Robust Error Detection And Concealment

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US Patent:
6404817, Jun 11, 2002
Filed:
Nov 20, 1997
Appl. No.:
08/975524
Inventors:
Angshuman Saha - Sunnyvale CA
Satish Soman - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04N 750
US Classification:
37524027, 3484252, 37524012, 386125, 714747
Abstract:
A video decoder is provided with robust error handling and concealment. In one embodiment, the video decoder detects syntactic, semantic, and coding errors in encoded slices of macroblocks. An error handler determines the number of remaining un-decoded macroblocks in the corrupted slice and replaces these corrupted macroblocks using substitute DCT coefficient matrices and motion vectors. The zero-frequency DCT coefficient of each substitute matrix is set equal to the zero-frequency DCT coefficient of the last uncorrupted macroblock, while the higher frequency DCT coefficients are set equal to zero. The substitute motion vectors are provided from a concealment vector memory which buffers the motion vectors of the previous macroblock row. In this way, intelligent approximations are made for the missing macroblocks, effectively masking the video bitstream error.

Audio Decoder Core Mpeg-1/Mpeg-2/Ac-3 Functional Algorithm Partitioning And Implementation

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US Patent:
6430533, Aug 6, 2002
Filed:
Apr 17, 1998
Appl. No.:
09/062344
Inventors:
Mahadev S. Kolluru - Santa Clara CA
Satish S. Soman - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G10L 1900
US Classification:
704500, 704501
Abstract:
A digital audio decoder is described. The digital audio decoder includes: (i) an audio core which defines a hardware for sub-band synthesis and windowing during decoding of MPEG and AC-3 digital audio signals; (ii) an input RAM coupled to the audio core and configured to store discrete samples in preparation for the sub-band synthesis and the windowing and configured to store intermediate values that are calculated by the audio core during the sub-band synthesis and written back to the input RAM. A process of decoding MPEG and AC-3 digital audio signals is also described. The process includes: (i) providing a digital audio decoder including firmware and hardware that are configured to decode MPEG or AC-3 digital audio signals; (ii) receiving MPEG or AC-3 encoded digital audio signals; (iii) decoding at least partially the digital audio signals by the firmware using MPEG or AC-3 audio algorithms that precede sub-band synthesis and windowing; and (iv) performing the sub-band synthesis and the windowing on MPEG or AC-3 digital audio signals by the hardware, wherein for a period of time the decoding of the digital audio signals by the firmware and performing the sub-band synthesis and the windowing by the hardware are carried out simultaneously.

Method Of Addressing Sequential Data Packets From A Plurality Of Input Data Line Cards For Shared Memory Storage And The Like, And Novel Address Generator Therefor

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US Patent:
6684317, Jan 27, 2004
Filed:
Dec 21, 2001
Appl. No.:
10/026166
Inventors:
Xiaolin Wang - Concord MA
Satish Soman - Westboro MA
Benjamin Marshall - Stowe MA
Subhasis Pal - Winchester MA
Assignee:
Axiowave Networks, Inc. - Marlborough MA
International Classification:
G06F 1208
US Classification:
711218
Abstract:
A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.

Audio Decoder Core (Acore) Mpeg Sub-Band Synthesis Algorithmic Optimization

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US Patent:
6757658, Jun 29, 2004
Filed:
Apr 17, 1998
Appl. No.:
09/062346
Inventors:
Mahadev S. Kolluru - Santa Clara CA
Satish S. Soman - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G10L 1900
US Classification:
704500, 704201
Abstract:
A digital audio decoder is described. The digital audio decoder includes: (i) an audio core which defines hardware for matrixing and windowing during decoding of MPEG digital audio signals such that matrixing coefficients are multiplied by discrete modified sample values during the matrixing operation; and (ii) an input RAM coupled to the audio core and configured to store the discrete modified sample values calculated outside the audio core in preparation for the matrixing operation and configured to store intermediate values calculated by the audio core during the matrixing operation that are written back to the input RAM. The modified sample values represent either a summation of two samples of MPEG audio data or a difference of the two samples of MPEG audio data. A process of decoding MPEG digital audio signals in a digital audio decoder including a firmware and a hardware, both of which are configured to decode MPEG audio signals, is also described. The process includes: (i) receiving MPEG encoded digital audio signals; (ii) decoding at least partially the digital audio signals by the firmware using MPEG audio algorithms that precede matrixing and windowing; and (iii) generating modified sample values of MPEG audio data by the firmware for matrixing, the modified sample values represent either a summation of two samples of MPEG audio data or a difference of the two samples of MPEG audio data.

Method Of Scalable Non-Blocking Shared Memory Output-Buffered Switching Of Variable Length Data Packets From Pluralities Of Ports At Full Line Rate, And Apparatus Therefor

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US Patent:
6999464, Feb 14, 2006
Filed:
Aug 28, 2001
Appl. No.:
09/941144
Inventors:
Xiaolin Wang - Concord MA, US
Satish Soman - Westboro MA, US
Subhasis Pal - Hopkinton MA, US
Assignee:
Axiowave Networks, Inc. - Marlborough MA
International Classification:
H04L 12/28
H04L 12/56
US Classification:
370412, 370413, 370415, 370417, 370419
Abstract:
A novel scalable-port non-blocking shared-memory output-buffered variable length queued data switching method and apparatus wherein successive data in each of a plurality of queues of data traffic is distributed to corresponding cells of each of successive memory channels in striped fashion across a shared memory space.

Method Of And Operating Architectural Enhancement For Multi-Port Internally Cached Dynamic Random Access Memory (Ampic Dram) Systems, Eliminating External Control Paths And Random Memory Addressing, While Providing Zero Bus Contention For Dram Access

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US Patent:
61382191, Oct 24, 2000
Filed:
Mar 27, 1998
Appl. No.:
9/049567
Inventors:
Satish S. Soman - Shrewsbury MA
Subhasis Pal - Winchester MA
Assignee:
Nexabit Networks LLC - Marlboro MA
International Classification:
G06F 1314
US Classification:
711149
Abstract:
A technique and system for eliminating bus contention in multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, while eliminating the need for external control paths and random memory addressing, through the use of data header destination bits and a novel dedication of reduced size slot buffers to separate DRAM banks and similarly dedicated I/O data read resource ports, particularly useful for relatively short ATM message networking and the like, wherein all system I/O resources are enabled simultaneously to write complete ATM messages into a single slot buffer, and also for SONET Cross Connect and WDM messages.

System And Method For Motion Vector Extraction And Computation Meeting 2-Frame Store And Letterboxing Requirements

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US Patent:
63109182, Oct 30, 2001
Filed:
Aug 29, 1997
Appl. No.:
8/921400
Inventors:
Angshuman Saha - Milpitas CA
Satish Soman - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H04N 712
H04B 166
US Classification:
37524016
Abstract:
A system and method for motion vector extraction and computation is embodied in an architecture adapted to overlap a data extraction process with a computation process and to provide 2-frame store decode with letterbox scaling capability, to extract a plurality of parameters usable for calculating a motion vector, and to compute motion vectors. The architecture is adapted to compute vertical and horizontal components of motion vectors in back-to-back cycles. The architecture includes a motion vector compute pipeline which, in a preferred embodiment includes a delta compute engine, a raw vector compute engine, a motion vector with respect to top left corner of picture block, or a combination of these logic circuits. The delta compute engine is adapted to generate a delta from a motion code and a motion residual and to compute a predicted motion vector in consideration of a motion vector of a previous macroblock. The raw vector compute engine is adapted to generate a raw vector from a delta and a predicted motion vector.

Architecture For Decoding Mpeg Compliant Video Bitstreams Meeting 2-Frame And Letterboxing Requirements

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US Patent:
62890530, Sep 11, 2001
Filed:
Jul 31, 1997
Appl. No.:
8/904084
Inventors:
Surya P. Varanasi - Tracy CA
Satish Soman - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
A04N 732
US Classification:
37524017
Abstract:
A system and method for performing motion compensation in an MPEG video decoder. The system comprises a horizontal half pixel compensation arrangement including multiple adders and multiplexers which perform horizontal half pixel compensation using an addition function, a division function, and a modulo function on pixel data. The system also includes a register bank which provides the ability to store an array of reference data when vertical half pixel compensation is required. The system also includes a verical half pixel compensation arrangement, which also includes multiple adders and multiplexers which perform vertical half pixel compensation using an addition function, a division function, and a modulo function on pixel data. Reference data and odd pixel data is transferred into and within the system in a predetermined arrangement. Reference and odd pel data may comprise either luma or chroma data.
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Satish S Soman from Cupertino, CA, age ~64 Get Report