Paul Blinzer

8487943, Jul 16, 2013

Dec 15, 2008

12/335258

Paul Blinzer - Bellevue WA, US
Phil Mummah - Palo Alto CA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 15/16
G06F 13/14

345504, 345502, 345503, 345520

Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced. A processor executes application software and driver software. The driver software includes first and second driver components for respectively controlling operation of the first and second graphics subsystems.

8578129, Nov 5, 2013

Dec 14, 2011

13/325282

Paul Blinzer - Bellevue WA, US
Leendert Peter Van Doorn - Austin TX, US
Gongxian Jeffrey Cheng - Toronto, CA
Elene Terry - Los Altos CA, US
Thomas Roy Woller - Austin TX, US
Arshad Rahman - Richmond Hill, CA

Advanced Micro Devices, Inc. - Sunnyvale CA
ATI Technologies ULC - Markham, Ontario

G06F 12/00

711206

In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.

8595386, Nov 26, 2013

Aug 3, 2009

12/534351

Paul Blinzer - Bellevue WA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 3/00

710 9

A peripheral device can be powered off when not in use by redirecting accesses to the peripheral device's configuration space from the peripheral device to a memory located separate from the peripheral device. A method for redirecting accesses includes copying the current contents of the configuration space to the memory. Accesses to the configuration space are redirected to the memory, whereby the memory services the accesses to the configuration space. After the redirection is enabled, the peripheral device can be powered off. When the peripheral device needs to be used again, it is powered on and the contents of the memory are copied to the configuration space. The configuration space can then resume servicing configuration space accesses.

20110216078, Sep 8, 2011

Mar 4, 2010

12/717265

Paul Blinzer - Bellevue WA, US

G06F 15/16

345502

Method, system, and apparatus provides for the processing of video and/or graphics data using a combination of first graphics processing circuitry and second graphics processing circuitry without losing state information while transferring the processing between the first and second graphics processing circuitry. The video and/or graphics data to be processed may be, for example, supplied by an application running on a processor such as host processor. In one example, an apparatus includes at least one GPU that includes a plurality of single instruction multiple data (SIMD) execution units. The GPU is operative to execute a native function code module. The apparatus also includes at least a second GPU that includes a plurality of SIMD execution units having a same programming model as the plurality of SIMD execution units on the first GPU. Furthermore, the first and second GPUs are operative to execute the same native function code module. The native code function module causes the first GPU to provide state information for the at least second GPU in response to a notification from a first processor, such as a host processor, that a transition from a current operational mode to a desired operational mode is desired (e.g., one GPU is stopped and the other GPU is started). The second GPU is operative to obtain the state information provided by the first GPU and use the state information via the same native function code module to continue processing where the first GPU left off. The first processor is operatively coupled to the at least first and at least second GPUs.

20120147021, Jun 14, 2012

Nov 4, 2011

13/289260

Jeffrey Gongxian CHENG - Toronto, CA
Paul BLINZER - Bellevue WA, US
Mark HUMMEL - Franklin MA, US
Leendert Peter VAN DOORN - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06T 1/00

345522

A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.

20120188258, Jul 26, 2012

Nov 4, 2011

13/289304

Rex MCCRARY - Oviedo FL, US
Michael Houston - Cupertino CA, US
Philip J. Rogers - Pepperell MA, US
Gongxian Jeffrey Cheng - Toronto, CA
Mark Hummel - Franklin MA, US
Paul Blinzer - Bellevue WA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 15/16

345502

A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.

20120229481, Sep 13, 2012

Dec 2, 2011

13/310162

Rex McCrary - Oviedo FL, US
Michael Clair Houston - Cupertino CA, US
Philip J. Rogers - Pepperell MA, US
Gongxian Jeffrey Cheng - Toronto, CA
Mark Hummel - Franklin MA, US
Charles Roberts Moore - Saratoga CA, US
Leendert Peter Van Doorn - Austin TX, US
Paul Blinzer - Bellevue WA, US

ATI Technologies ULC - Markham
Advanced Micro Devices, Inc. - Sunnyvale CA

G06T 1/00

345522

A method, system, and computer program product are disclosed for providing improved access to accelerated processing device compute resources to user mode applications. The functionality disclosed allows user mode applications to provide commands to an accelerated processing device without the need for kernel mode transitions in order to access a unified ring buffer. Instead, applications are each provided with their own buffers, which the accelerated processing device hardware can access to process commands. With full operating system support, user mode applications are able to utilize the accelerated processing device in much the same way as a CPU.

20120249559, Oct 4, 2012

Apr 4, 2012

13/439569

Oleksandr KHODORKOVSKY - Toronto, CA
Paul BLINZER - Bellevue WA, US
Korhan ERENBEN - Mississauga, CA
Leonard Martin BERK - Toronto, CA
Min ZHANG - Richmond Hill, CA

ATI Technologies ULC - Markham
Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1/32
G06F 15/16
G06F 15/00

345502, 345522, 713323

A method of operating a processing device is provided. The method includes, responsive to an idle state of the processing device, transitioning the processing device to a substantially disabled state. The processing device, for example, may be a graphics processing unit (GPU). Transitioning the processing device to a substantially disabled state upon detection of an idle state may result in power savings. Corresponding systems and computer program products are also provided.