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Luigi Capodieci

from Redwood City, CA
Age ~63
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Connected to:
Angela Capodiferro, 40Jean A Capodieci, 85Yajaira Capodiferro, 63Ronald A Capodilupo, 66Marco Capodivacca, 56Aristomenis W Capogeannis, 51Daniela M Capogna, 45Betty Capolino, 75Steven Capolino, 41Gennaro N Capolongo, 64

Luigi Capodieci Phones & Addresses

  • 1322 Virginia Ave, Redwood City, CA 94061
  • Madison, WI
  • 315 Van Ness Ave, Santa Cruz, CA 95060 (831) 471-2784
  • 1 Amd Pl, Sunnyvale, CA 94085
  • Mountain View, CA
  • Menlo Park, CA

Publications

Us Patents

Etch Bias Distribution Across Semiconductor Wafer

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US Patent:
6458606, Oct 1, 2002
Filed:
May 11, 2001
Appl. No.:
09/854272
Inventors:
Marina V. Plat - San Jose CA
Luigi Capodieci - Sunnyvale CA
Scott A. Bell - San Jose CA
Todd Lukanc - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01R 3126
US Classification:
438 14
Abstract:
Test wafers used in the production of semiconductor wafers include a plurality of active structures which form operational circuitry of the test wafer. The active structures are densely populated in some areas of the test wafer and sparsely populated in other areas of the test wafer. It has been observed that critical dimensions such as etch bias and slope profiles of identical structures vary depending on whether the structure is formed in a densely or sparsely populated region. Dummy structures are formed on the test wafer so as to uniformly distribute the density of structures across the test wafer.

Characterization And Synthesis Of Opc Structures By Fourier Space Analysis And/Or Wavelet Transform Expansion

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US Patent:
6492066, Dec 10, 2002
Filed:
May 28, 1999
Appl. No.:
09/321089
Inventors:
Luigi Capodieci - Sunnyvale CA
Christopher A. Spence - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G03F 900
US Classification:
430 5, 716 21
Abstract:
A method ( ) of characterizing optical proximity correction designs includes performing a mathematical transform ( ) on a first feature ( ) and a second feature ( ) each having a core portion ( ) and a first OPC design and a second OPC design applied thereto, respectively. The method ( ) further includes obtaining a metric (162) for the transformed first and second features, wherein the metric is based upon a capability of a pattern transfer system which will utilize masks employing the first and second features ( ) as a patterns thereon. One of the first feature or the second feature is then selected ( ) based upon an application of the metric to the first and second transformed features ( ), thereby selecting the one of the first feature or the second feature which provides for a better pattern transfer performance.

Method And Apparatus For Generating Masks Utilized In Conjunction With Dipole Illumination Techniques

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US Patent:
6553562, Apr 22, 2003
Filed:
Nov 5, 2001
Appl. No.:
09/985621
Inventors:
Luigi Capodieci - Santa Cruz CA
Juan Andres Torres Robles - Milpitas CA
Lodewijk Hubertus Van Os - Eindhoven, NL
Assignee:
ASML Masktools B.V. - Veldhoven
ASM Lithography B.V. - Veldhoven
International Classification:
G06F 1750
US Classification:
716 19, 716 21, 430 5
Abstract:
A method of generating complementary masks for use in a multiple-exposure lithographic imaging process. The method includes the steps of identifying âhorizontalâ critical features and âverticalâ critical features from a plurality of features forming a layout; identifying interconnection areas which are areas in which one of the horizontal critical features or the vertical critical features contacts another feature of the layout; defining a set of primary parameters on the basis of the proximity of the plurality of features relative to one another; and generating an edge modification plan for each interconnection area based on the primary parameters. A horizontal mask pattern is then generated by compiling the horizontal critical features, a first shield plan for the vertical critical features and the interconnection areas containing a horizontal critical feature modified by the edge modification plan. A vertical mask pattern is then generated by compiling the vertical critical features, a second shield plan for the horizontal critical features and the interconnection areas containing a vertical critical feature modified by the edge modification plan.

Utilizing Electrical Performance Data To Predict Cd Variations Across Stepper Field

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US Patent:
6562639, May 13, 2003
Filed:
Nov 6, 2001
Appl. No.:
09/993166
Inventors:
Anna Minvielle - San Jose CA
Luigi Capodieci - Santa Cruz CA
Christopher Spence - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2166
US Classification:
438 14
Abstract:
In order to determine an amount of critical dimension variation to expect across a surface of a final production wafer, a plurality of test structures are formed on a test wafer. The test structures are preferably of a type commonly found on the final production wafer and may for example, include transistors, ring oscillators, resistors and/or diodes. Electrical parameter testing of the test structures is next conducted in order to obtain one or more electrical performance values for each test structure. For example, the electrical performance values may correspond to processing speed, drive current, and/or off-state current of the test structures. A correlation between the electrical performance values and expected critical dimension variations is then performed and a report is generated providing the expected critical dimension variations across the surface of the wafer. Expected critical dimension variations may be accounted for by varying characteristics of devices used during a photolithographic transfer process to the final production wafers.

Microdevice Fabrication Method Using Regular Arrays Of Lines And Spaces

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US Patent:
6583041, Jun 24, 2003
Filed:
May 1, 2000
Appl. No.:
09/562502
Inventors:
Luigi Capodieci - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 214763
US Classification:
438618, 438128, 438129, 438599
Abstract:
A method of fabricating a microdevice having the steps of forming a first regular array of lines and spaces from a first layer of material deposited on a substrate; patterning the first regular array of lines and spaces to form a first portion of a microdevice component; providing an intermediate layer over the first portion of the microdevice component; forming a second regular array of lines and spaces from a second layer of material deposited on the intermediate layer; patterning the second regular array of lines and spaces to form a second portion of the microdevice component; and forming contact holes in the intermediate layer to establish conductivity between the first portion of the microdevice component and the second portion of the microdevice component.

Lithographic Photomask And Method Of Manufacture To Improve Photomask Test Measurement

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US Patent:
6974652, Dec 13, 2005
Filed:
Nov 3, 2003
Appl. No.:
10/699748
Inventors:
Todd P. Lukanc - San Jose CA, US
Luigi Capodieci - Santa Cruz CA, US
Bhanwar Singh - Morgan Hill CA, US
Christopher A. Spence - Sunnyvale CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01F009/00
US Classification:
430 5
Abstract:
A photomask for use in a lithographic process and a method of making a photomask are disclosed. A mask blank including a substrate, a sacrificial conductive layer disposed over the substrate and a radiation shielding layer disposed over the sacrificial conductive layer can be provided. Structures are then formed from the radiation shielding layer to define a pattern. Measurement of parameters associated with the structures are made with a measurement tool and, during the measuring, the sacrificial conductive layer provides a conductive plane to dissipate charge transferred to the mask by the measurement tool.

Optical Proximity Correction (Opc) Technique Using Generalized Figure Of Merit For Photolithograhic Processing

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US Patent:
6978438, Dec 20, 2005
Filed:
Oct 1, 2003
Appl. No.:
10/677154
Inventors:
Luigi Capodieci - Santa Cruz CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G06F017/50
US Classification:
716 21, 716 19
Abstract:
A method and associated computer program for making optical proximity corrections for a reticle layout topology. Edge segments of the reticle layout topology are manipulated to generate a corrected reticle layout accounting for optical distortions and, based on the corrected reticle layout, a plurality of individual figure of merit values are generated. A generalized figure of merit (GFOM) using the plurality of individual figure of merit values is then generated.

Microdevice Having Non-Linear Structural Component And Method Of Fabrication

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US Patent:
6995433, Feb 7, 2006
Filed:
Mar 2, 2004
Appl. No.:
10/791250
Inventors:
Todd P. Lukanc - San Jose CA, US
Sarah N. McGowan - San Francisco CA, US
Luigi Capodieci - Santa Cruz CA, US
Bhanwar Singh - Morgan Hill CA, US
Joerg Reiss - Sunnyvale CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 29/94
H01L 31/062
US Classification:
257366, 257401
Abstract:
A microdevice for forming a part of an integrated circuit and method for fabricating are disclosed. The microdevice can include a first conductive region and a second conductive region having a channel region interposed therebetween. The mircodevice has a channel region controlling component disposed over the channel region and separated therefrom by at least one dielectric layer. The channel region controlling component has a non-linear structural characteristic derived from a non-linear structural characteristic of a photo resist feature used as an etch mask for the channel region controlling component.
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Luigi Capodieci from Redwood City, CA, age ~63 Get Report