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Kanon Lily W Liu

from Arcadia, CA
Age ~73
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Also known as:
Kanon Lily Liu, Kanon I Liu, Kanon J Liu, Ka Non Liu, Liu Kanon, Lily Liu
Phone and address:
1818 Lee Ave, Arcadia, CA 91006
(626) 445-5049
Related to:
Wei Liu, 88Choa K Liu, 49Charlene C Liu, 46Linda W Liu, 37Jean L Horenstein, 46Craig I Horenstein, 49Frank Tzyymin Lin, 73Shihang Liu, 44Jun W Fu, 79Lily W Liu, 71Eric Q Wei, 47Kuang Chan Wei, 69
Connected to:
Abby Liu, 37Alba Liu, 48Alina Y Liu, 53Annan R Liu, 53Antong Liu, 35Anwei Liu, 62Bai Liu, 66Bao Liu, 51Baoxian Liu, 54Bella C Liu, 101

Kanon Liu Phones & Addresses

  • 1818 Lee Ave, Arcadia, CA 91006 (626) 445-5049 (626) 353-8788
  • Rowland Heights, CA
  • San Diego, CA
  • Goleta, CA
  • Cambridge, OH
  • Rowland Heights, CA
  • Los Angeles, CA
  • 1818 Lee Ave, Arcadia, CA 91006 (626) 353-8788

Work

Company: Raytheon vision systems - Goleta, CA 2005 Position: Principal electrical engineer

Education

School / High School: California Polytech University Kellogg West Center- Pomona, CA 2004 Specialities: Certificate in Design

Skills

analog IC / mixed-signal IC design and c... • MATLAB/Simulink • and Cadence SKILL Programming

Languages

Mandarin • Taiwanese

Ranks

Certificate: Cadence Skill Language Programming Vic6.1.6 Class Completion Certificate

Interests

Social Services • Education • Environment • Science and Technology • Disaster and Humanitarian Relief • Animal Welfare • Arts and Culture • Health

Emails

k***[email protected]

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Kanon Liu Photo 1

Analog Ic Design Contractor

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Location:
Arcadia, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Encore Semi
Analog Ic Design Contractor
Raytheon Jan 2005 - Jun 2014
Principal Electrical Engineer
Telasic Communications Sep 2002 - Oct 2004
Mixed-Signal Ic Design Engineer
Vitesse Semiconductor Oct 1998 - Jul 2002
Analog Ic Design Engineer
Teradyne Jul 1995 - Aug 1998
Analog Asic Development Engineer
Education:
University at Buffalo 1980 - 1988
Doctorates, Doctor of Philosophy, Computer Engineering, Philosophy
Skills:
Analog
Ic
Simulations
Integrated Circuit Design
Cadence
Engineering
Testing
Electronics
Project Management
Hands on Experience In Design of Trans Impedance Amplifier With Capacit
Interests:
Social Services
Education
Environment
Science and Technology
Disaster and Humanitarian Relief
Animal Welfare
Arts and Culture
Health
Languages:
Mandarin
Taiwanese
Certifications:
Cadence Skill Language Programming Vic6.1.6 Class Completion Certificate
Cadence Training Services at San Jose, Ca, License 8/25/2014 - 8/29/2014
License 8/25/2014 - 8/29/2014
Kanon Liu Photo 2

Kanon Liu Arcadia, CA

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Work:
RAYTHEON VISION SYSTEMS
Goleta, CA
2005 to 2014
Principal Electrical Engineer
TELASIC COMMUNICATIONS
El Segundo, CA
2002 to 2004
Mixed-Signal IC Design Engineer
VITESSE SEMICONDUCTOR CORPORATION
Camarillo, CA
1998 to 2002
Analog IC Design Engineer
Education:
California Polytech University Kellogg West Center
Pomona, CA
2004
Certificate in Design
State University of New York at Buffalo
Buffalo, NY
Ph.D. in Electrical and Computer Engineering
National Cheng-Kung University
Tainan, Taiwan
MSEE in Electrical Engineering
National Cheng-Kung University
Tainan, Taiwan
BSEE in Electrical Engineering
Skills:
analog IC / mixed-signal IC design and characterization<br/>designing chips with a track record of 100% first pass success<br/>Cadence Virtuoso Analog IC Design Environment tools<br/>Verilog HDL/Verilog-A/Verilog-AMS, MATLAB/Simulink, and Cadence SKILL Programming

Publications

Us Patents

Read Out Integrated Circuit

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US Patent:
8373458, Feb 12, 2013
Filed:
Nov 17, 2009
Appl. No.:
12/619870
Inventors:
Kanon Liu - Arcadia CA, US
Bryan W. Kean - Fairfax VA, US
James F. Asbrock - Oceanside CA, US
Assignee:
Raytheon Company - Waltham MA
International Classification:
H03L 7/00
US Classification:
327143
Abstract:
According to one embodiment, a circuit comprises a Capacitive Trans-Impedance Amplifier (CTIA) configured to receive a current pulse at an input and convert the current pulse to a voltage step. The voltage step is directed to a first signal path and a second signal path. When the voltage step exceeds a first threshold, the first signal path directs an enable pulse to the second signal path. The second signal path generates an output pulse when the voltage step exceeds a second threshold and the enable pulse is enabled. The second signal path comprises a first, a second, and a third amplifier to increase detection of the voltage step by the second signal path.

Low Noise, Low Power And High Bandwidth Capacitive Feedback Trans-Impedance Amplifier With Differential Fet Input And Bipolar Emitter Follower Feedback

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US Patent:
20090108942, Apr 30, 2009
Filed:
Oct 30, 2007
Appl. No.:
11/980294
Inventors:
Kanon Liu - Arcadia CA, US
James F. Asbrock - Oceanside CA, US
International Classification:
H03F 3/16
US Classification:
330300
Abstract:
A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low output impedance and some degree of output inductive peaking, and the CTIA differential output is buffered by the bipolar npn emitter follower in the CTIA feedback loop such as the open-loop high voltage gain is maintained without being affected by output loads.
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Kanon Lily W Liu from Arcadia, CA, age ~73 Get Report