Inventors:
Michiel Victor Paul Kruger - Berkeley CA, US
Bayram Yenikaya - San Jose CA, US
Anwei Liu - Fremont CA, US
Abdurrahman Sezginer - Monte Sereno CA, US
Wolf Staud - Redwood City CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 19/00
G03F 1/00
G21K 5/00
US Classification:
716 53, 716 54, 716 55, 716119, 700 98, 700120, 700121, 430 5, 378 35
Abstract:
According to various embodiments of the invention systems and methods for multiple pattern lithography, wherein a target layout pattern that is not capable of being printed in one lithography step is decomposed into multiple patterns that are printable in one lithography operation and, when appropriate, a continuous junction is utilized for where patterns overlap. In a further embodiment, where a continuous junction is not utilized, a splice is utilized at overlap locations. In yet another embodiment, where splices are utilized for overlap locations, identifying where critical nets are located in the target layout pattern, determining how close a component of the critical net is to a splice, and changing the target layout pattern as to avoid the condition of a component of the critical net being in proximity to a splice. In another embodiment of the invention, where splices are utilized at overlap locations, placing a landing pad of contacts or vias at the same location as the splice.
