James G Mittel

6356142, Mar 12, 2002

Sep 20, 2000

09/666037

James Gregory Mittel - Lake Worth FL

Motorola, Inc. - Schaumburg IL

H03K 500

327553, 327552

A digital tuning circuit ( ) for a filter ( ) has a filter input and a filter output and employs a switchable element array ( ). The filter includes a tuning signal generator ( ) that generates a tuning signal ( ) that is delivered to the filter input and a clock circuit ( ) that generates a periodic stream of pulses. The digital tuning circuit includes a delay circuit ( ), a phase comparator ( ) and an integrating up-down counter ( ). The delay circuit ( ) is responsive to the tuning signal generator ( ) and delays the tuning signal ( ) by a predetermined amount corresponding to the nominal delay through the filter ( ). The integrating up-down counter ( ) counts pulses in a first direction when the phase comparator ( ) generates the first value and counts pulses in a second direction, opposite from the first direction, when the phase comparator ( ) generates the second value. The integrating up-down counter ( ) generates a binary word having a value corresponding to a number of counts that the integrating up-down counter ( ) performs and is coupled to the switchable element array ( ) so that a number of switchable elements is electrically coupled to the filter ( ). The number of switchable elements corresponds to the value of the binary word.

6560447, May 6, 2003

Mar 5, 2001

09/798216

Mahibur Rahman - Boynton Beach FL
Christopher T. Thomas - San Diego CA
Robert Schweickert - Mesa AZ
James Mittel - Lake Worth FL

Motorola, Inc. - Schaumburg IL

H04B 106

4552321, 4552401, 375319, 375345

A DC offset correction circuit ( ) provides DC offset correction within a receiver ( ) for receiving and processing a radio frequency signal ( ) within a radio communication system ( ). The DC offset correction circuit ( ) includes a feedback loop ( ) for shifting a digital signal ( ) by a programmable amount; and a coarse DC offset correction path ( ) coupled to the feedback loop ( ) for performing coarse DC offset correction.

6606359, Aug 12, 2003

Jul 26, 2000

09/626466

Manbir Nag - Coral Springs FL
James Mittel - Lake Worth FL

Motorola, INC - Schaumburg IL

H04L 2508

375348, 375319, 455296

A digital DC offset correction circuit ( ) provides DC offset correction within a receiver ( ) using an area-optimum, rapid acquisition cellular multi-protocol digital dc offset correction scheme. The digital DC offset correction circuit ( ) includes an integrator ( ), a low pass filter ( ), a decimator ( ), a digital to analog converter codeword clamp ( ), and a digital to analog converter ( ).

6839387, Jan 4, 2005

Mar 7, 2000

09/517113

James Gregory Mittel - Lake Worth FL, US

Motorola, Inc. - Schaumburg IL

H04B 1406
H03M 300

375247, 375316, 341143

A sigma-delta converter operates over a predetermined bandwidth and includes a feedback loop comprising a forward path and a feedback path. The forward path includes, in series, a summer, a filter, and a comparator. The comparator produces an output signal that is fed back to a negative input of the summer via the feedback path. The sigma-delta converter also includes at least one instability generator positioned in the forward path and/or the feedback path. The instability generator generates one or more out-of-band instabilities in the feedback loop to substantially improve the in-band signal-to-noise performance of the converter for input signal amplitudes near a low end of the converter's dynamic range. The converter may be employed as an A/D converter, a D/D converter, or a D/A converter in a receiver and/or a transmitter of a wireless communication device.

7397291, Jul 8, 2008

Jan 10, 2007

11/621844

James G. Mittel - Boynton Beach FL, US
James J. Riches - Lake Worth FL, US

Freescale Semiconductor, Inc. - Austin TX

H03K 3/70
H03K 3/023
H03M 1/66

327176, 327291, 327172, 327165, 341144, 341143

A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

52300943, Jul 20, 1993

May 7, 1992

7/879397

Philip A. Kitching - N. Lauderdale FL
James G. Mittel - Boynton Beach FL

Motorola, Inc. - Schaumburg IL

H04B 110

4551832

In a heterodyne receiver having more than one selectable receive frequency and having at least one intermediate frequency circuit (102) capable of operation on at least two intermediate frequencies, a method for selecting one of the at least two intermediate frequencies is shown. The selection method includes selecting (402) one of the more than one selectable receive frequency, and then selecting (408, 410, 504, 506, 510, 512) at least one of the at least two intermediate frequencies for each of the at least one intermediate frequency circuit in response to the selected receive frequency. The selection of the intermediate frequency for each of the at least one intermediate frequency circuit is made such that the selected intermediate frequency does not cause the generation of one or more undesirable spurious frequencies as a result of mixing the selected receive frequency and the selected intermediate frequency.

51535793, Oct 6, 1992

Feb 21, 1991

7/657936

Kenneth D. Fisch - Delray Beach FL
James G. Mittel - Boynton Beach FL
Winfield J. Brown - Lantana FL

Motorola, Inc. - Schaumburg IL

H04Q 700

34082522

A paging receiver is provided which digitizes and stores received analog voice messages. The stored voice message may be retrieved by using a first switch for a normal playback mode, or by using a second switch for a fast forward and fast reverse playback mode. The fast forward and fast reverse playback modes are achieved by sequentially retrieving every N(th) message bit stored in memory.

57349746, Mar 31, 1998

Mar 27, 1996

8/625435

Edgar Herbert Callaway - Boca Raton FL
James Gregory Mittel - Lake Worth FL
Vance Howard Peterson - Boca Raton FL
Burkhard Dick - Hamburg, DE
Knud Holtvoeth - Hamburg, DE
Wilfried Knop - Appen, DE

Motorola, Inc. - Schaumburg IL

H04B 106

4552341

A receiver (100) for receiving an input signal and generating an output signal therefrom has a switchable gain circuit (104) with a stepwise variable gain control (118), a local oscillator (106) and an automatic gain control (AGC) detector (114) with a response for detecting a level of the output signal and generating an AGC signal indicative of the level of the output signal and a state machine (116) being responsive to the AGC signal generating a control signal at the stepwise variable gain control to increase or decrease a gain of the switchable gain circuit in discrete stepwise steps.