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James L Broseghini

from Austin, TX
Deceased
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Also known as:
James Louis Broseghini, Jim Broseghini, James I
Phone and address:
6901 Fence Line Dr, Austin, TX 78749
(512) 892-4756
Related to:
Justin Broseghini, 35Bill Broseghini, 99Thomas Broseghini, 61Rose M Broseghini
Connected to:
Regina L Broselle, 58Suzanne M Brosell, 60George R Brosemann, 68Cheryl L Brosemer, 44Donna Brosemer, 82Frederick G Brosen, 70Michael T Brosenne, 77Justin V Brosette, 44Nicole C Brosey, 37Stuart A Brosey, 59

James Broseghini Phones & Addresses

  • 6901 Fence Line Dr, Austin, TX 78749 (512) 892-4756
  • Leander, TX
  • Rock Springs, WY
  • Dripping Springs, TX
  • Orinda, CA
  • Travis, TX
  • 6901 Fence Line Dr, Austin, TX 78749 (512) 751-4317

Work

Company: Sigma research Jan 2000 Position: Chief technolgist hardware design

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: University of Wyoming 1976 to 1983 Specialities: Electrical Engineering

Skills

Mixed Signal • Hardware Architecture • Ic • Analog • Semiconductors • Asic • Cmos • Embedded Systems • Verilog • Physical Design • Microcontrollers • Floorplanning • Silicon • Lvs

Emails

j***[email protected]

Industries

Design

Resumes

Resumes

James Broseghini Photo 1

Chief Technolgist Hardware Design

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Location:
Austin, TX
Industry:
Design
Work:
Sigma Research
Chief Technolgist Hardware Design
Ion Geophysical Jun 1995 - Jan 2000
Team Lead and Group Manager
Motorola Sep 1983 - Jun 1995
Senior Design Engineer
Education:
University of Wyoming 1976 - 1983
Masters, Master of Science In Electrical Engineering, Electrical Engineering
Skills:
Mixed Signal
Hardware Architecture
Ic
Analog
Semiconductors
Asic
Cmos
Embedded Systems
Verilog
Physical Design
Microcontrollers
Floorplanning
Silicon
Lvs

Publications

Us Patents

Sensor

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US Patent:
7114366, Oct 3, 2006
Filed:
Mar 16, 2000
Appl. No.:
09/936630
Inventors:
Ben Jones - Austin TX, US
Scott T. Dupuie - Buda TX, US
Jeffrey Allen Blackburn - Austin TX, US
Richard A. Johnson - Buda TX, US
Michael L. Abrams - Houston TX, US
James Broseghini - Austin TX, US
Mauricio A. Zavaleta - Austin TX, US
Mark E. Burchfield - Austin TX, US
Roger Maher - Dublin, IE
Burton A. Devolk - Austin TX, US
Frank Mayo - Houston TX, US
Assignee:
Input / Output Inc. - Stafford TX
International Classification:
G01D 18/00
US Classification:
73 101, 73 137
Abstract:
A system for acquiring environmental information measurements. The 5 system () utilize a sensor, () a front-end circuit, () a loop filter (), a switch controller (), and a reduced-order loop control circuit to provide reliable data measurements while providing robust system behavior. The system further includes a sensor simulator () for simulating the operation of the sensor () and testing the operation of the front-end circuit () and the loop filter ().

Multiplier Having A Reduced Number Of Partial Product Calculations

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US Patent:
51193256, Jun 2, 1992
Filed:
Dec 4, 1990
Appl. No.:
7/622029
Inventors:
J. Greg Viot - Austin TX
James L. Broseghini - Austin TX
Eytan Hartung - Austin TX
John P. Dunn - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 752
US Classification:
364760
Abstract:
An adder circuit that has an encoded carry input, where a bit position weight of the carry input is two, allows the adder circuit to selectively concurrently add a data value of two to a first and a second input data operand of the adder circuit. The adder circuit is also able to add the first and second input data operands with a second carry input that is not encoded. A recoded multiplier combines two partial product calculations into one calculation during only a first partial product calculation operation by using the adder circuit. Partial product calculations are reduced in number during a multiply operation of a data processor.

Circuit And Method For Evaluating Fuzzy Logic Rules

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US Patent:
52631257, Nov 16, 1993
Filed:
Jun 17, 1992
Appl. No.:
7/899968
Inventors:
J. Greg Viot - Austin TX
James M. Sibigtroth - Round Rock TX
James L. Broseghini - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1518
US Classification:
395 51
Abstract:
A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single "REV" software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are separated from consequences of each of the rules by a buffer address. To evaluate the antecedents, an ALU (52) subtracts an antecedent in memory (32) from a current antecedent stored in an accumulator (58). Subsequently, a swap logic (46) provides control information to assign a minimum value as a rule strength of the rule. Similarly, a maximum rule strength is required during evaluation of the consequences. ALU (52) subtracts a consequence in memory (32) from a consequence stored in accumulator (58). Depending on a result, swap logic (46) provides control information to assign a maximum rule strength to the consequences of the evaluated rule.

Method And Apparatus For Performing Restricted Modulo Arithmetic

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US Patent:
52491480, Sep 28, 1993
Filed:
Nov 26, 1990
Appl. No.:
7/617725
Inventors:
Michael Catherwood - Austin TX
Greg Viot - Austin TX
James L. Broseghini - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 738
US Classification:
364746
Abstract:
A digital data processor is capable of performing limited modulo arithmetic. The base, M, of the modulo arithmetic to be preformed by the processor must be equal to 2. sup. X, where X is an integer. The method and apparatus is particularly useful for generating addresses for a circular buffer or queue data structure and avoids both the large amount of hardware required for general modulo arithmetic and the software overhead associated with the use of linear arithmetic to generate modulo addresses. According to this method, X is represented as a first digital value. This representation of X is ANDed with a second digital data value (an offset). The result is then ADDed linearly with a third digital data value (a current address with the buffer). During this addition process, certain carry-out signals are inhibited from propagating, according to the digital representation of X.

Method And Apparatus For Scan Testing With Extended Test Vector Storage In A Multi-Purpose Memory System

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US Patent:
57614890, Jun 2, 1998
Filed:
Apr 17, 1995
Appl. No.:
8/422467
Inventors:
James L. Broseghini - Austin TX
John A. Langan - Austin TX
Thomas J. Poterek - Austin TX
Assignee:
Motorola Inc. - Shaumburg IL
International Classification:
G06F 1126
US Classification:
395568
Abstract:
A data processor (12) has built-in circuitry for scan testing certain circuits. The data processor generates and stores test vectors in a memory system (22) normally used for data and instruction storage. These vectors can be much larger than the size of any scan chain. During testing, the stored vectors are automatically routed to the circuits to be tested (36, 38) and the outputs compared to a benchmark. The data processor (12) need not pause to generate additional test vectors. Therefore, the data processor (12) can use a single circuit to generate scan data and compress scan results with minimal timing or size implications.

Method And Apparatus For Generating Pseudorandom Numbers Or For Performing Data Compression In A Data Processor

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US Patent:
54167833, May 16, 1995
Filed:
Aug 9, 1993
Appl. No.:
8/103614
Inventors:
James L. Broseghini - Austin TX
James G. Viot - Austin TX
Donald H. Lenhert - Manhattan KS
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1127
US Classification:
371 223
Abstract:
A method and apparatus for generating pseudo-random numbers or for performing data compression in a data processor (12). In one form, the present invention generates pseudo-random numbers which are used to provide scan input data bits during built-in-self-test (BIST) scan testing. The present invention then performs data compression on the scan output data received back from the circuits under test (73-75). In one embodiment, the BIST scan testing of data processor (12) is performed in a special "background self-test mode". Central processing unit (CPU) 20 is used to generate the pseudo-random numbers and to perform the data compression. CPU 20 also functions as a standard CPU when in a normal operating mode.

Circuit And Method For Determining Membership In A Set During A Fuzzy Logic Operation

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US Patent:
52952290, Mar 15, 1994
Filed:
Jun 17, 1992
Appl. No.:
7/899975
Inventors:
J. Greg Viot - Austin TX
James M. Sibigtroth - Round Rock TX
James L. Broseghini - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1518
US Classification:
395 51
Abstract:
A circuit (14) and method which determine a degree of membership of an input in a membership set during a fuzzy logic operation. The degree of membership is calculated by a single "MEM" software instruction. The MEM instruction determines whether the system input has a degree of membership of zero, of a saturation level, or of some value in between. An operand assignment circuit (50) and an ALU (56) allow circuit (14) to determine the degree of membership more quickly. Assignment circuit (50) determines a multiplier for a multiplication operation based on a number of significant bits in the values to be multiplied. If the multiplier is smaller than the multiplicand, shorter multiplication operations may be performed. Additionally, ALU (56) operates in a split mode of operation which is able to perform two eight bit subtraction or multiplication operations concurrently which also results in these operations being performed more efficiently.

Method And Apparatus For Unstacking Registers In A Data Processing System

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US Patent:
56405480, Jun 17, 1997
Filed:
Oct 19, 1992
Appl. No.:
7/962560
Inventors:
John A. Langan - Austin TX
Thomas J. Poterek - Austin TX
James L. Broseghini - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 930
G06F 946
US Classification:
395561
Abstract:
A method and apparatus for unstacking registers in a data processing system (100). In one form, the present invention is a more time efficient solution to the problem of unstacking and stacking registers (154-158) during interrupt processing in a data processing system (100). By taking advantage of the fact that pulling a register value off of the stack does not change any of the values stored in the memory which is being used as the stack, the present invention reduces the unstacking and stacking each time that two interrupts are processed back to back with no non-interrupt processing in between. The present invention eliminates the unstacking of the program counter register (158) and the restacking of registers (154-158) by changing the value of the stack pointer register (161) without any corresponding stacking or unstacking operation.
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James L Broseghini from Austin, TXDeceased Get Report