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Gunnar Gaubatz

from Los Gatos, CA
Age ~51
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Also known as:
Gunnar Guabatz
Connected to:
Allison D Gaubatz, 45Stephen P Gaubatz, 67Thomas D Gaubatz, 52Tommy L Gaubatz, 66Brad Gaubert, 46James J Gaubert, 58Nathan M Gaubert, 30Sophie Gaubert, 110Pierre Gaubil, 59Joseph R Gaubinger, 93

Gunnar Gaubatz Phones & Addresses

  • Los Gatos, CA
  • 1086 Byerley Ave, San Jose, CA 95125
  • Los Angeles, CA
  • Worcester, MA
  • Santa Clara, CA

Work

Company: Intel corporation Feb 2012 Address: Santa Clara, CA Position: Component design engineer

Education

School / High School: Worcester Polytechnic Institute 2002 to 2007

Skills

Embedded Systems • Algorithms • Embedded Software • Verilog • Cryptography • Computer Architecture • Fpga • C++ • Signal Processing • Asic • Soc • C • Xilinx • Systemverilog • 68K Assembly • Rtl Design • Very Large Scale Integration • Field Programmable Gate Arrays • X86 Assembly • Software Development • Debugging • Programming • Ethernet • Hardware Architecture • Matlab • Simulink • Vivado • Firmware • Joint Test Action Group • High Level Synthesis • Computer Arithmetic • I2C • Refactoring • Hardware/Software Co Design • Functional Modeling • Zynq • Python • Universal Asynchronous Receiver/Transmit... • Spi • Semiconductors • Objective C • Coding Theory • Algorithm Analysis • Vlsi

Languages

German • English

Industries

Aviation & Aerospace

Resumes

Resumes

Gunnar Gaubatz Photo 1

Software Engineer

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Location:
Palo Alto, CA
Industry:
Aviation & Aerospace
Work:
Intel Corporation - Santa Clara, CA since Feb 2012
Component Design Engineer
Education:
Worcester Polytechnic Institute 2002 - 2007
Worcester Polytechnic Institute 2000 - 2002
Fachhochschule München 1995 - 2000
Skills:
Embedded Systems
Algorithms
Embedded Software
Verilog
Cryptography
Computer Architecture
Fpga
C++
Signal Processing
Asic
Soc
C
Xilinx
Systemverilog
68K Assembly
Rtl Design
Very Large Scale Integration
Field Programmable Gate Arrays
X86 Assembly
Software Development
Debugging
Programming
Ethernet
Hardware Architecture
Matlab
Simulink
Vivado
Firmware
Joint Test Action Group
High Level Synthesis
Computer Arithmetic
I2C
Refactoring
Hardware/Software Co Design
Functional Modeling
Zynq
Python
Universal Asynchronous Receiver/Transmitter
Spi
Semiconductors
Objective C
Coding Theory
Algorithm Analysis
Vlsi
Languages:
German
English

Publications

Us Patents

System And Method For Cryptography Processing Units And Multiplier

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US Patent:
7725624, May 25, 2010
Filed:
Dec 30, 2005
Appl. No.:
11/323993
Inventors:
Wajdi K. Feghali - Boston MA, US
William C. Hasenplaugh - Jamaica Plain MA, US
Gilbert M. Wolrich - Framingham MA, US
Daniel R. Cutter - Maynard MA, US
Vinodh Gopal - Westboro MA, US
Gunnar Gaubatz - Worcester MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/00
G06F 5/00
G06F 15/00
H04L 29/06
US Classification:
710 52, 710 20, 712 32, 712 37, 713150
Abstract:
In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.

System And Method For Multi-Precision Division

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US Patent:
7738657, Jun 15, 2010
Filed:
Aug 31, 2006
Appl. No.:
11/469243
Inventors:
Vinodh Gopal - Westboro MA, US
Matt Bace - North Andover MA, US
Gunnar Gaubatz - Worcester MA, US
Gilbert M. Wolrich - Framingham MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 9/00
US Classification:
380 28, 708650, 708651, 708652, 708653, 708654
Abstract:
The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Techniques For Merging Tables

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US Patent:
7801299, Sep 21, 2010
Filed:
Sep 22, 2006
Appl. No.:
11/534330
Inventors:
Gunnar Gaubatz - Worcester MA, US
William C. Hasenplaugh - Jamaica Plain MA, US
Bradley A. Burres - Waltham MA, US
Wajdi Feghali - Boston MA, US
Kirk Yap - Boston MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 9/30
US Classification:
380 28
Abstract:
Techniques are described herein to overlay and merge any number of tables of equivalent size and structure. Bits or patterns of bits that are similar among tables may be set to a voltage value representative of respective logical ‘0’ or ‘1’. The bits that are different among the tables may be connected to either the value of a table selection signal or its inverse.

Determining Message Residue Using A Set Of Polynomials

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US Patent:
7827471, Nov 2, 2010
Filed:
Oct 12, 2006
Appl. No.:
11/581055
Inventors:
William C. Hasenplaugh - Jamaica Plain MA, US
Brad A. Burres - Waltham MA, US
Gunnar Gaubatz - Worcester MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03M 13/00
US Classification:
714781, 714758
Abstract:
A method is described for use in determining a residue of a message. The method includes loading at least a portion of each of a set of polynomials derived from a first polynomial, g(x), and determining the residue using a set of stages. Individual ones of the stages apply a respective one of the derived set of polynomials to data output by a preceding one of the set of stages.

Method For Simultaneous Modular Exponentiations

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US Patent:
7925011, Apr 12, 2011
Filed:
Dec 14, 2006
Appl. No.:
11/610919
Inventors:
Vinodh Gopal - Westboro MA, US
Erdinc Ozturk - Worcester MA, US
Kaan Yuksel - Worcester MA, US
Gunnar Gaubatz - Worcester MA, US
Wajdi Feghali - Boston MA, US
Gilbert M. Wolrich - Framingham MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 9/00
US Classification:
380 30, 380 28, 380 44, 380 45, 380277, 709228, 713100
Abstract:
The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder (v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number (q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y).

Multiplying Two Numbers

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US Patent:
7930337, Apr 19, 2011
Filed:
Jun 27, 2006
Appl. No.:
11/476329
Inventors:
William C. Hasenplaugh - Jamaica Plain MA, US
Gunnar Gaubatz - Worcester MA, US
Vinodh Gopal - Westboro MA, US
Matthew M. Bace - North Andover MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/52
US Classification:
708625
Abstract:
Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba multiplication based on the values of the most significant bits of A and B.

Hardware Accelerator

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US Patent:
8020142, Sep 13, 2011
Filed:
Dec 14, 2006
Appl. No.:
11/610871
Inventors:
Gilbert M. Wolrich - Framingham MA, US
William Hasenplaugh - Jamaica Plain MA, US
Wajdi Feghali - Boston MA, US
Daniel Cutter - Maynard MA, US
Vinodh Gopal - Westboro MA, US
Gunnar Gaubatz - Worcester MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/44
G06F 9/45
G06F 7/38
US Classification:
717106, 717151, 717159, 717161, 708490
Abstract:
A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.

Cryptographic System, Method And Multiplier

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US Patent:
8073892, Dec 6, 2011
Filed:
Dec 30, 2005
Appl. No.:
11/323994
Inventors:
Wajdi K. Feghali - Boston MA, US
William C. Hasenplaugh - Jamaica Plain MA, US
Gilbert M. Wolrich - Framingham MA, US
Daniel R. Cutter - Maynard MA, US
Vinodh Gopal - Westboro MA, US
Gunnar Gaubatz - Worcester MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 7/52
US Classification:
708631, 708603, 708627
Abstract:
In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
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Gunnar Gaubatz from Los Gatos, CA, age ~51 Get Report