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David Welland Phones & Addresses

  • 112 32Nd St, Austin, TX 78705 (512) 477-5316
  • 1204 Claire Ave, Austin, TX 78703 (512) 422-2315
  • 4215 Avenue A, Austin, TX 78751 (512) 467-6156
  • 112 Old Dock Rd, Falmouth, MA 02540
  • 32 Black Beach Rd, Falmouth, MA 02540 (508) 457-0872
  • Westwood Hills, KS

Business Records

Name / Title
Company / Classification
Phones & Addresses
David Welland
Director
SILICON LABORATORIES INC
400 W Cesar Chavez, Austin, TX 78701
2390 E Camelback Rd, Phoenix, AZ 85016
Director 400 W Cesar Chavez, Austin, TX 78701
David Welland
Director, Vice President, Principal
THE SOOCH FOUNDATION
Membership Organizations, Nec, Nsk
600 W 7 St, Austin, TX 78701
David Welland
Board of Directors
Sooch Nav
Nonprofit Trust Management
600 W 7 St, Austin, TX 78701
(512) 472-5747

Publications

Us Patents

Digital Isolation System With Data Scrambling

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US Patent:
6359983, Mar 19, 2002
Filed:
Mar 4, 1998
Appl. No.:
09/034687
Inventors:
Andrew W. Krone - Austin TX
Jeffrey W. Scott - Austin TX
Navdeep S. Sooch - Austin TX
David R. Welland - Austin TX
Assignee:
Silicon Laboratories, Inc. - Austin TX
International Classification:
H04M 100
US Classification:
37939901, 37939902, 379416, 379412, 379405, 379382, 375285
Abstract:
A method and apparatus are provided for reducing the amplitude of signals that often are inadvertently coupled to a telephone line from an isolation barrier system, or that cause undesirable interference within the circuitry of the isolation barrier system. Such signals have undesirable peaks in the frequency domain (spectral peaks) due to the existence of periodicities in the data signal that is transmitted across the isolation barrier. Such spectral peaks are reduced by this invention, which comprises randomizing or scrambling the data signal before it crosses the isolation barrier, and descrambling the data after it has crossed the isolation barrier. In one embodiment, the data signal is scrambled by combining it with a random bit stream (or a pseudo random bit stream), which effectively âwhitensâ the resulting scrambled signal, thus removing spectral peaks that exist in the original data signal. After the scrambled signal passes across the isolation barrier, it is descrambled by reversing the original scrambling operation. In preferred embodiments, both the scrambling and the descrambling steps are performed by combining the incoming signal with synchronized pseudo-random bit patterns using âexclusive-orâ logical operations.

Direct Digital Access Arrangement Circuitry And Method For Connecting To Phone Lines

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US Patent:
6385235, May 7, 2002
Filed:
Mar 4, 1998
Appl. No.:
09/035175
Inventors:
Jeffrey W. Scott - Austin TX
Navdeep S. Sooch - Austin TX
David R. Welland - Austin TX
Assignee:
Silicon Laboratories, Inc. - Austin TX
International Classification:
H04B 138
US Classification:
375220, 375222, 37939902, 379412, 379413
Abstract:
An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors.

Method And Apparatus For Providing Coarse And Fine Tuning Control For Synthesizing High-Frequency Signals For Wireless Communications

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US Patent:
6388536, May 14, 2002
Filed:
Jun 27, 2000
Appl. No.:
09/604228
Inventors:
David R. Welland - Austin TX
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H03L 708
US Classification:
331177R, 331117 R, 331177 V, 331 36 C, 331 1 A, 327107, 327159, 455260, 455262
Abstract:
A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a more general terms, a frequency synthesizer is disclosed having a first variable and a second capacitance circuits and frequency control circuitry to coarsely tune the output frequency by adjusting the first control signal and to finely tune the output frequency by adjusting the second control signal.

Isolation System With Digital Communication Across A Capacitive Barrier

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US Patent:
6389061, May 14, 2002
Filed:
May 15, 2000
Appl. No.:
09/567721
Inventors:
Jeffrey W. Scott - Austin TX
Navdeep S. Sooch - Austin TX
David R. Welland - Austin TX
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H04M 318
US Classification:
375220, 375258, 375359, 375377, 379412
Abstract:
An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors.

Call Progress Monitor Circuitry And Method For A Communication System

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US Patent:
6389134, May 14, 2002
Filed:
Mar 4, 1998
Appl. No.:
09/035779
Inventors:
Timothy J. Dupuis - Austin TX
George Tyson Tuttle - Austin TX
Jeffrey W. Scott - Austin TX
Navdeep S. Sooch - Austin TX
David R. Welland - Austin TX
Assignee:
Silicon Laboratories, Inc. - Austin TX
International Classification:
H04M 100
US Classification:
37937301, 37937302, 37937303, 37937304, 37937305, 379252
Abstract:
A call progress monitor circuit is disclosed for a digital DAA in which digital information is transmitted across an isolation barrier from phone line side circuitry to powered side circuitry. In particular, the call progress monitor circuit of the present invention converts oversampled digital transmit and receive data into analog transmit and receive signals and then combines them to produce a call progress signal that is provided to be fed to a speaker driver circuit. In addition, the call progress signal in one embodiment is filtered with a low pass filter. The call progress monitor circuit in one embodiment includes oversampled digital-to-analog converters, a summing circuit, and a low pass filter. Corresponding methods for monitoring the progress of a call utilizing oversampled digital transmit and receive signals are also disclosed.

Framed Delta Sigma Data With Unlikely Delta Sigma Data Patterns

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US Patent:
6408034, Jun 18, 2002
Filed:
Mar 4, 1998
Appl. No.:
09/034682
Inventors:
Andrew W. Krone - Austin TX
Jerrell P. Hein - Austin TX
Jeffrey W. Scott - Austin TX
Navdeep S. Sooch - Austin TX
David R. Welland - Austin TX
Assignee:
Silicon Laboratories, Inc. - Austin TX
International Classification:
H04L 706
US Classification:
375285, 375365
Abstract:
A communication system having a framing pattern to frame data to be transmitted to a phone line is provided. The data may be framed on one side of an isolation barrier and a clock signal may be extracted from the framed data stream on the other side of the barrier. The data to be framed is provided from an output of a delta-sigma modulator and the framing pattern utilized is a pattern that is unlikely to match the data stream output of the modulator. Thus, an erroneous detection of the framing pattern is unlikely to occur. The framing pattern is chosen to correspond to the expected modulator output for a full scale input signal that is at a frequency higher than the maximum actual frequency of the input data provided to the modulator.

Capacitive Isolation System With Digital Communication And Power Transfer

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US Patent:
6430229, Aug 6, 2002
Filed:
Apr 22, 1997
Appl. No.:
08/837714
Inventors:
Jeffrey W. Scott - Austin TX
Navdeep S. Sooch - Austin TX
David R. Welland - Austin TX
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H03M 302
US Classification:
375285, 341110, 341143, 37937301, 379377
Abstract:
An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors.

Digital Isolation System With Hybrid Circuit In Adc Calibration Loop

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US Patent:
6442213, Aug 27, 2002
Filed:
Mar 4, 1998
Appl. No.:
09/035180
Inventors:
Andrew W. Krone - Austin TX
Timothy J. Dupuis - Austin TX
Jeffrey W. Scott - Austin TX
Navdeep S. Sooch - Austin TX
David R. Welland - Austin TX
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H03M 106
US Classification:
375285, 341118, 341120
Abstract:
An improved digital capacitive isolation barrier system is provided that is suitable for use in a telephone or modem where the locally powered circuits must be effectively isolated from the public telephone system, while permitting data transfer across the barrier. In particular, an automatic ADC offset calibration system is provided for determining the magnitude of the ADC offset signal required in the system during a calibration operation, and for providing the calibrated ADC offset signal during normal operation of the isolation barrier system. A modified hybrid circuit is provided for isolating the system input from the telephone line during calibration, and for completing the calibration loop. Fixed bias signals are also provided for the ADC and for a DAC in the system. In a preferred embodiment, the ADC is located on the isolated side of the isolation barrier, while the integrator and register that determine and hold the offset signal are located on the powered side of the isolation barrier.
David R Welland from Austin, TX, age ~69 Get Report