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Daesik Song

from San Jose, CA
Age ~54
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Also known as:
Dae Sik Song
Related to:
Seoyeon Song
Connected to:
Agnes S Song, 71Anne I Song, 61Bo Y Song, 60Chae O Song, 70Chai H Song, 68Chunyu Song, 56Cong Song, 61Dale Y Song, 39Danning Song, 33Dean H Song, 46

Daesik Song Phones & Addresses

  • San Jose, CA
  • Sunnyvale, CA

Work

Company: Micron technology Dec 2008 Position: Staff design eng.

Education

Degree: MS School / High School: Korea University 1988 to 1996 Specialities: Electrical Engineering

Skills

Dram • Semiconductors • Ic • Nand Flash • Cmos • Mixed Signal • Soc • Verilog • Asic • Analog • Debugging

Industries

Semiconductors

Resumes

Resumes

Daesik Song Photo 1

Director

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Location:
Berkeley, CA
Industry:
Semiconductors
Work:
Micron Technology since Dec 2008
Staff Design Eng.
ST Microelectronics Oct 2003 - Sep 2007
Senior Design Engineer
Hynix 1996 - 2002
Design Engineer
Education:
Korea University 1988 - 1996
MS, Electrical Engineering
Skills:
Dram
Semiconductors
Ic
Nand Flash
Cmos
Mixed Signal
Soc
Verilog
Asic
Analog
Debugging

Publications

Us Patents

Slew Rate Modulation

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US Patent:
20130147532, Jun 13, 2013
Filed:
Dec 9, 2011
Appl. No.:
13/316167
Inventors:
Daesik Song - Sunnyvale CA, US
International Classification:
H03K 5/12
US Classification:
327170
Abstract:
Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.

Memory Devices Configured To Latch Data For Output In Response To An Edge Of A Clock Signal Generated In Response To An Edge Of Another Clock Signal

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US Patent:
20190258400, Aug 22, 2019
Filed:
Apr 30, 2019
Appl. No.:
16/398646
Inventors:
- Boise ID, US
Qiang Tang - Cupertino CA, US
Ali Feiz Zarrin Ghalam - Sunnyvale CA, US
Hoon Choi - Santa Clara CA, US
Daesik Song - Sunnyvale CA, US
Assignee:
MICRON TECHNOLOGY, INC. - BOISE ID
International Classification:
G06F 3/06
G11C 16/26
G11C 16/32
G11C 7/10
G11C 7/22
G06F 12/0802
G06F 12/02
Abstract:
Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

Memory Devices Configured To Latch Data For Output In Response To An Edge Of A Clock Signal Generated In Response To An Edge Of Another Clock Signal

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US Patent:
20180292990, Oct 11, 2018
Filed:
Jun 12, 2018
Appl. No.:
16/006192
Inventors:
- BOISE ID, US
Qiang Tang - Cupertino CA, US
Ali Feiz Zarrin Ghalam - Sunnyvale CA, US
Hoon Choi - Santa Clara CA, US
Daesik Song - Sunnyvale CA, US
Assignee:
MICRON TECHNOLOGY, INC. - BOISE ID
International Classification:
G06F 3/06
G11C 16/32
G11C 16/26
G11C 7/22
G11C 7/10
G06F 12/0802
Abstract:
Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

Latching Data For Output At An Edge Of A Clock Signal Generated In Response To An Edge Of Another Clock Signal

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US Patent:
20170285938, Oct 5, 2017
Filed:
Mar 30, 2016
Appl. No.:
15/084979
Inventors:
- BOISE ID, US
Qiang Tang - Cupertino CA, US
Ali Feiz Zarrin Ghalam - Sunnyvale CA, US
Hoon Choi - Santa Clara CA, US
Daesik Song - Sunnyvale CA, US
Assignee:
MICRON TECHNOLOGY, INC. - BOISE ID
International Classification:
G06F 3/06
G11C 16/26
G06F 12/08
G11C 16/32
Abstract:
In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

Slew Rate Modulation

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US Patent:
20150092499, Apr 2, 2015
Filed:
Dec 11, 2014
Appl. No.:
14/567903
Inventors:
- Boise ID, US
Daesik Song - Sunnyvale CA, US
International Classification:
G11C 16/24
G11C 7/12
US Classification:
36518523, 36518911
Abstract:
Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.
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Daesik Song from San Jose, CA, age ~54 Get Report