Professional Records
License Records
Boon Jin Ooi
License #:
065018695 - Expired
Issued Date:
Nov 10, 1987
Expiration Date:
Sep 30, 2015
Type:
Licensed Certified Public Accountant
Boon Ooi Phones & Addresses
-
3227 W Lake Sammamish Pkwy SE, Bellevue, WA 98008 (425) 679-6155
-
3227 Lake Sammamish Ln, Bellevue, WA 98008 (425) 679-6155
-
Beaverton, OR
-
19640 Bainter Ave, Los Gatos, CA 95030 (425) 679-6155
-
22233 Antioch Downs Ct, Tualatin, OR 97062
-
639 Carrera Ln, Lake Oswego, OR 97034 (503) 635-7258
-
Newport Beach, CA
-
Kiona, WA
-
Santa Clara, CA
Resumes
Resumes
Boon Ooi
View pagePublications
Us Patents
Method And Structure For Forming Vertical Semiconductor Interconnection
View pageUS Patent:
50579070, Oct 15, 1991
Filed:
Jun 11, 1990
Appl. No.:
7/535838
Inventors:
Boon K. Ooi - Cupertino CA
Norman L. Gould - San Jose CA
Norman L. Gould - San Jose CA
Assignee:
National Semiconductor Corp. - Santa Clara CA
International Classification:
H01L 3902
H01L 2328
H01L 2348
H01L 2328
H01L 2348
US Classification:
357 80
Abstract:
An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure. In one embodiment, the portion of the tape opposite the area to which the integrated circuit die is to be inner lead bonded includes secondary metallization regions. Suitable vias in the tape contact these secondary metallization regions to selected ones of the metallic leads which are to be inner lead bonded to the integrated circuit.