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Aurobindo Dasgupta Phones & Addresses

  • 10702 Scotland Well Dr, Austin, TX 78750 (512) 506-8472
  • 8102 Tallyho Trl, Austin, TX 78729
  • 11215 Research Blvd, Austin, TX 78759 (512) 346-9146
  • Amherst, MA
  • Sunderland, MA

Work

Position: Soc power estimation and optimization

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Massachusetts Amherst 1996 to 1996 Specialities: Computer Engineering

Skills

Soc • Low Power Design • Silicon Validation • Eda • Asic • Rtl Design • Vlsi • Static Timing Analysis • Verilog • Systemverilog • Processors • Tcl • Debugging • Physical Design • Functional Verification

Industries

Semiconductors

Resumes

Resumes

Aurobindo Dasgupta Photo 1

Soc Power Estimation And Optimization

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Location:
Austin, TX
Industry:
Semiconductors
Work:

Soc Power Estimation and Optimization
Education:
University of Massachusetts Amherst 1996 - 1996
Doctorates, Doctor of Philosophy, Computer Engineering
Indian Institute of Technology, Madras 1958 - 1958
Bachelors, Bachelor of Technology, Engineering
Skills:
Soc
Low Power Design
Silicon Validation
Eda
Asic
Rtl Design
Vlsi
Static Timing Analysis
Verilog
Systemverilog
Processors
Tcl
Debugging
Physical Design
Functional Verification

Publications

Us Patents

Logic With State Retentive Sleep Mode

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US Patent:
7649385, Jan 19, 2010
Filed:
Aug 7, 2006
Appl. No.:
11/500820
Inventors:
Aurobindo Dasgupta - Austin TX, US
Mark Schuelein - Tempe AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 19/00
US Classification:
326 93, 326 33, 326 95
Abstract:
Embodiments disclosed herein provide sleep mode solutions for retaining state information while reducing power in a logic block.

Registers For An Enhanced Idle Architectural State

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US Patent:
20070147572, Jun 28, 2007
Filed:
Dec 28, 2005
Appl. No.:
11/320429
Inventors:
Aurobindo Dasgupta - Austin TX, US
Amit Bhalerao - Bangalore, IN
International Classification:
G11C 19/00
US Classification:
377064000
Abstract:
Some embodiments of the invention include apparatus, systems, and methods to force values to output nodes of registers of at least one circuit unit of a device during an idle state to reduce leakage power in the circuit unit. Other embodiments are described and claimed.

Iterative, Noise-Sensitive Method Of Routing Semiconductor Nets Using A Delay Noise Threshold

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US Patent:
6480998, Nov 12, 2002
Filed:
Apr 18, 2000
Appl. No.:
09/551322
Inventors:
Pradipto Mukherjee - Austin TX
Aurobindo Dasgupta - Austin TX
David T. Blaauw - Austin TX
David R. Bearden - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1750
US Classification:
716 13, 716 6, 716 12
Abstract:
The invention relates to a new method of guidance for routing of nets in an integrated circuit model wherein all nets are first approximately routed, as with Steiner routing, and victim nets with functional delay noise above predetermined thresholds are identified. Each victim net is then detail routed. For each victim net detail routed, a set of least noise aggressive neighboring nets is selected. Segments of those neighboring nets are assigned tracks adjacent to the victim net in such a way as to maximize utilization of the victim nets neighboring tracks, thereby reducing noise induced on the victim net and maximizing use of available space on the semiconductor. The process is then repeated until there are no additional victim nets, at which point the remaining nets are detail routed.
Aurobindo Dasgupta from Austin, TX, age ~57 Get Report