Zongwu Te Tang

7496884, Feb 24, 2009

Aug 25, 2006

11/510415

Weiping Fang - Fremont CA, US
Huijuan Zhang - Cupertino CA, US
Yibing Wang - Sunnyvale CA, US
Zongwu Tang - Pleasanton CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716 21, 716 4, 716 5, 716 19, 716 20, 430 5, 430 30

A system that verifies a simulated wafer image against an intended design. During operation, the system receives a design. Next, the system generates a skeleton from the design, wherein the skeleton specifies cell placements and associated bounding boxes for the cell placements, but does not include geometries for the cell placements. The system then computes environments for cell placements based on the skeleton. Next, the system generates templates for cell placements, wherein a template for a cell placement specifies the cell placement and the environment surrounding the cell placement. The system then generates the simulated wafer image by performing model-based simulations for cell placements associated with unique templates.

7636904, Dec 22, 2009

Oct 20, 2006

11/584356

Hua Song - San Jose CA, US
ZongWu Tang - Pleasanton CA, US

SYNOPSYS, Inc. - Mountain View CA

G06F 17/50

716 5, 716 4, 716 20, 716 21

A computer is programmed to perform lithography simulation at a number of locations in a transverse direction relative to a length of a feature of an IC design, to obtain simulated intensities at the locations. The computer is further programmed to determine constants of a predetermined formula that models a trend of the simulated intensities as a function of distance (in the transverse direction), by curve-fitting. The computer is also programmed to compute a value (“CD predictor”) based on the just-determined constants, the formula and a known threshold intensity for a given position along the feature's length. The just-described process, of lithography-simulation, followed by curve-fitting, followed by CD predictor computation, is repeatedly performed to obtain a number of CD predictors at a corresponding number of positions along the feature's length. The CD predictors are used to identify a position of a critical dimension, for use in, for example, layout verification.

7679872, Mar 16, 2010

Jul 21, 2008

12/176801

Jamil Kawa - Campbell CA, US
Subarnarekha Sinha - Menlo Park CA, US
Min-Chun Tsai - San Jose CA, US
ZongWu Tang - Pleasanton CA, US
Qing Su - Sunnyvale CA, US

Synopsys, Inc. - Mountain View CA

H02H 9/04
H02H 9/00

361 56

Embodiments of an interface circuit are described. This interface circuit includes an input pad, a control node and a transistor, which has three terminals. A first terminal is electrically coupled to the input pad and a second terminal is electrically coupled to the control node. Moreover, the interface circuit includes a micro-electromechanical system (MEMS) switch, which is electrically coupled to the input pad and the control node, where the MEMS switch is in parallel with the transistor. In the absence of a voltage applied to a control terminal of the MEMS switch, the MEMS switch is closed, thereby electrically coupling the input pad and the control node. Furthermore, when the voltage is applied to the control terminal of the MEMS switch, the MEMS switch is open, thereby electrically decoupling the input pad and the control node.

8037428, Oct 11, 2011

May 29, 2008

12/129617

Yang-Shan Tong - Chung-ho, TW
Daniel Zhang - Milpitas CA, US
Linni Wei - Mountain View CA, US
Alex Miloslavsky - Sunnyvale CA, US
Wei-Chih Tseng - Fremont CA, US
Zongwu Tang - Pleasanton CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716 51, 716 52

One embodiment of the present invention provides a system that verifies an integrated circuit (IC) chip layout. During operation, the system receives a layout of an IC chip after the layout has gone through a place-and-route operation. Next, the system performs a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot. Next, for each detected lithography hotspot, the system compares the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores a set of known hotspot configurations. If so, the system corrects the lithography hotspot using correction guidance information associated with the hotspot configuration stored in the hotspot database. Otherwise, the system corrects the lithography hotspot by performing a local rip-up and reroute on the local routing pattern, iteratively, until achieving convergence or given number of iterations.

8264065, Sep 11, 2012

Oct 23, 2009

12/605102

Qing Su - Sunnyvale CA, US
Min Ni - Santa Clara CA, US
Zongwu Tang - Pleasanton CA, US
Jamil Kawa - Campbell CA, US
James D. Sproch - Monte Sereno CA, US

Synopsys, Inc. - Mountain View CA

H01L 29/40
H01L 23/053
H01L 23/12
H01L 23/48
H01L 23/52
H01L 23/62

257621, 257355, 257700, 257774, 257E21597, 257E23011

Roughly described, an antenna diode is formed at least partially within the exclusion zone around a TSV, and is connected to the TSV by way of a metal 1 layer conductor at the same time that the TSV is connected to either the gate poly or a diffusion region of one or more transistors placed outside the exclusion zone.

8458635, Jun 4, 2013

Dec 4, 2009

12/631167

Min Ni - Santa Clara CA, US
Zongwu Tang - Pleasanton CA, US
Qing Su - Sunnyvale CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716119, 716100, 716123

A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed.

8566754, Oct 22, 2013

Nov 21, 2008

12/275887

Kent Y. Kwang - Saratoga CA, US
Daniel Zhang - Milpitas CA, US
Zongwu Tang - Pleasanton CA, US
Subarnarekha Sinha - Menlo Park CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716 52, 716 53

One embodiment of the present invention provides a system that automatically processes manufacturing hotspot information. During operation, the system receives a pattern clip associated with a manufacturing hotspot in a layout, wherein the pattern clip comprises a set of polygons in proximity to the manufacturing hotspot's location. Next, the system determines if the pattern clip matches a known manufacturing hotspot configuration. If the pattern clip does not match a known manufacturing hotspot configuration, the system then performs a perturbation process on the pattern clip to determine a set of correction recommendations to eliminate the manufacturing hotspot. By performing the perturbation process, the system additionally determines ranges of perturbation to the set of polygons wherein the perturbed pattern clip does not eliminate the manufacturing hotspot. Subsequently, the system stores the set of correction recommendations and the ranges of perturbation into a manufacturing hotspot database.

8578313, Nov 5, 2013

Apr 24, 2008

12/109118

Zongwu Tang - Pleasanton CA, US
Daniel Zhang - San Jose CA, US
Alex Miloslavsky - Sunnyvale CA, US
Subarnarekha Sinha - Menlo Park CA, US
Jingyu Xu - Beijing, CN
Kent Y. Kwang - Saratoga CA, US
Kevin A. Beaudette - Orleans CA, US

Synopsys, Inc. - Mountain View CA

G06F 17/50

716112

One embodiment of the present invention provides a system that generates a pattern-clip-based hotspot database for performing automatic pattern-clip-based layout verification. During operation, the system receives a list of pattern clips which specify manufacturing hotspots to be avoided in a layout, wherein each pattern clip comprises a set of geometries in proximity to each other. Next, for each pattern clip, the system perturbs the pattern clip to determine a first range of variations for the constituent set of geometries wherein the perturbed pattern clip no longer causes a manufacturing hotspot. The system then extracts a set of correction guidance descriptions from the first range of variations for correcting the pattern clip. Subsequently, the system stores the pattern clip and the set of correction guidance descriptions in the pattern-clip-based hotspot database.