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Zoltan Tibor Hidvegi

from Austin, TX
Age ~54
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Also known as:
Zoltan T Hidvegi, Tibor Hidvegi, Tiborne Hidvegi, Zoltan L, Zoltan I
Phone and address:
7401 Sage Oak Trl, Austin, TX 78759
Related to:
Marta Hidvegi
Connected to:
Linda S Hidy, 68Patrick K Hidy, 80Shannon Hidy, 36Kelsey Hieatt, 30Barry R Hieb, 80Christine M Hieb, 73Jesse D Hieb, 42Kathryn A Hieb, 69Kayla L Hieb, 34Paul A Hieb, 69

Zoltan Hidvegi Phones & Addresses

  • 7401 Sage Oak Trl, Austin, TX 78759
  • 9417 Great Hills Trl, Austin, TX 78759
  • 7205 Hart Ln, Austin, TX 78731
  • Leander, TX
  • Wimberley, TX
  • 1517 Jerusalem Dr, Round Rock, TX 78664 (512) 252-7107
  • 1517 Jerusalem Dr, Round Rock, TX 78664

Business Records

Name / Title
Company / Classification
Phones & Addresses
Zoltan Hidvegi
Manager
ZBM INVESTMENT, LLC
700 Lavaca St STE 1401, Austin, TX 78701

Publications

Us Patents

Modeling Asynchronous Behavior From Primary Inputs And Latches

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US Patent:
7885801, Feb 8, 2011
Filed:
Jul 7, 2008
Appl. No.:
12/168888
Inventors:
Zoltan T. Hidvegi - Round Rock TX, US
Yee Ja - Round Rock TX, US
Bradley S. Nelson - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
703 15, 716 6
Abstract:
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.

Partitioning And Scheduling Uniform Operator Logic Trees For Hardware Accelerators

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US Patent:
8495535, Jul 23, 2013
Filed:
Nov 28, 2011
Appl. No.:
13/305156
Inventors:
Zoltan T. Hidvegi - Round Rock TX, US
Michael D. Moffitt - Austin TX, US
Matyas A. Sustik - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716106
Abstract:
A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e. g. , an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e. g. , OR gates), the functional equivalence of the model is preserved.

Modeling Asynchronous Behavior From Primary Inputs And Latches

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US Patent:
20070198238, Aug 23, 2007
Filed:
Feb 23, 2006
Appl. No.:
11/360906
Inventors:
Zoltan Hidvegi - Round Rock TX, US
Yee Ja - Round Rock TX, US
Bradley Nelson - Austin TX, US
International Classification:
G06F 17/50
US Classification:
703015000
Abstract:
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.
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Zoltan Tibor Hidvegi from Austin, TX, age ~54 Get Report