Ziyad Sami Hakura

7053901, May 30, 2006

Dec 11, 2003

10/732445

Michael Brian Cox - Menlo Park CA, US
Ziyad S. Hakura - Palo Alto CA, US
John S. Montrym - Cupertino CA, US
Brad W. Simeral - San Francisco CA, US
Brian Keith Langendorf - Benicia CA, US
Blanton Scott Kephart - Dallas TX, US
Franck R. Diard - Mountain View CA, US

NVIDIA Corporation - Santa Clara CA

G06T 1/00

345503, 345506

Embodiments of the invention accelerate at least one special purpose processor, such as a GPU, or a driver managing a special purpose processor, by using at least one co-processor. Advantageously, embodiments of the invention are fault-tolerant in that the at least one GPU or other special purpose processor is able to execute all computations, although perhaps at a lower level of performance, if the at least one co-processor is rendered inoperable. The co-processor may also be used selectively, based on performance considerations.

7206902, Apr 17, 2007

Aug 17, 2004

10/921026

Ziyad S. Hakura - Mountain View CA, US
Brian Keith Langendorf - Benicia CA, US
Stefano A. Pescador - Sunnyvale CA, US
Radoslav Danilak - Santa Clara CA, US
Brad W. Simeral - San Francisco CA, US

NVIDIA Corporation - Santa Clara CA

G06F 12/00

711137, 711118, 711154, 712207, 712237

A system, apparatus, and method are disclosed for predicting accesses to memory. In one embodiment, an exemplary apparatus comprises a processor configured to execute program instructions and process program data, a memory including the program instructions and the program data, and a memory processor. The memory processor can include a speculator configured to receive an address containing the program instructions or the program data. Such a speculator can comprise a sequential predictor for generating a configurable number of sequential addresses. The speculator can also include a nonsequential predictor configured to associate a subset of addresses to the address and to predict a group of addresses based on at least one address of the subset, wherein at least one address of the subset is unpatternable to the address.

7248261, Jul 24, 2007

Dec 15, 2003

10/736953

Ziyad S. Hakura - Palo Alto CA, US

NVIDIA Corporation - Santa Clara CA

G06T 15/60

345426

The present invention provides for accelerating the generation of graphical images that include shadow effects by, for example, reducing the amount of data transmitted and/or stored necessary to render graphics based on stencil shadow volumes. In one embodiment, an exemplary apparatus is configured to render shadows using stencil shadow volumes. The apparatus includes a memory to store a degree of shadowing for each sample. A co-processor, which is coupled to the memory, is configured to generate an indicator that represents a common degree of shadowing associated with the subset of samples. In some cases, the apparatus includes a graphics processing unit (“GPU”), which is coupled to the co-processor, that is configured to render one or more shadows for a computer-generated image based on the indicator.

7260686, Aug 21, 2007

Aug 17, 2004

10/920995

Ziyad S. Hakura - Mountain View CA, US
Radoslav Danilak - Santa Clara CA, US
Brad W. Simeral - San Francisco CA, US
Brian Keith Langendorf - Benicia CA, US
Stefano A. Pescador - Sunnyvale CA, US
Dmitry Vyshetsky - Cupertino CA, US

Nvidia Corporation - Santa Clara CA

G06F 12/00

711137

A system, apparatus, and method are disclosed for storing predictions as well as examining and using one or more caches for anticipating accesses to a memory. In one embodiment, an exemplary apparatus is a prefetcher for managing predictive accesses with a memory. The prefetcher can include a speculator to generate a range of predictions, and multiple caches. For example, the prefetcher can include a first cache and a second cache to store predictions. An entry of the first cache is addressable by a first representation of an address from the range of predictions, whereas an entry of the second cache is addressable by a second representation of the address. The first and the second representations are compared in parallel against the stored predictions of either the first cache and the second cache, or both.

7342590, Mar 11, 2008

May 9, 2003

10/435073

John M. Danskin - Cranston RI, US
Ziyad S. Hakura - Palo Alto CA, US
Edward L. Riegelsberger - Fremont CA, US
Jason M. Musicer - San Jose CA, US
Stephen D. Lew - Sunnyvale CA, US

Nvidia Corporation - Santa Clara CA

G06T 9/00
G06K 9/36

345555, 382232

Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.

7369126, May 6, 2008

Nov 17, 2006

11/561322

Ziyad S. Hakura - Palo Alto CA, US

Nvidia Corporation - Santa Clara CA

G06T 15/60

345426

The present invention provides for accelerating the generation of graphical images that include shadow effects by, for example, reducing the amount of data transmitted and/or stored necessary to render graphics based on stencil shadow volumes. In one embodiment, an exemplary apparatus is configured to render shadows using stencil shadow volumes. The apparatus includes a memory to store a degree of shadowing for each sample. A co-processor, which is coupled to the memory, is configured to generate an indicator that represents a common degree of shadowing associated with the subset of samples. In some cases, the apparatus includes a graphics processing unit (“GPU”), which is coupled to the co-processor, that is configured to render one or more shadows for a computer-generated image based on the indicator.

7441087, Oct 21, 2008

Aug 17, 2004

10/920610

Ziyad S. Hakura - Mountain View CA, US
Brian Keith Langendorf - Benicia CA, US
Stefano A. Pescador - Sunnyvale CA, US
Radoslay Danilak - Santa Clara CA, US
Brad W. Simeral - San Francisco CA, US

NVIDIA Corporation - Santa Clara CA

G06F 9/26
G06F 12/00

711137, 710244

A system, apparatus, and method are disclosed for managing predictive accesses to memory. In one embodiment, an exemplary apparatus is configured as a prediction inventory that stores predictions in a number of queues. Each queue is configured to maintain predictions until a subset of the predictions is either issued to access a memory or filtered out as redundant. In another embodiment, an exemplary prefetcher predicts accesses to a memory. The prefetcher comprises a speculator for generating a number of predictions and a prediction inventory, which includes queues each configured to maintain a group of items. The group of items typically includes a triggering address that corresponds to the group. Each item of the group is of one type of prediction. Also, the prefetcher includes an inventory filter configured to compare the number of predictions against one of the queues having the either the same or different prediction type as the number of predictions.

7450120, Nov 11, 2008

Dec 19, 2003

10/741115

Ziyad S. Hakura - Mountain View CA, US
Michael Brian Cox - Menlo Park CA, US
Brian K. Langendorf - Benicia CA, US
Brad W. Simeral - San Francisco CA, US

Nvidia Corporation - Santa Clara CA

G06T 15/40
G06F 15/16
G06T 1/20

345421, 345422, 345503, 345506

A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.