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Zhiguo Qian

from Chandler, AZ
Age ~46
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Connected to:
Amy Qian, 36Ashley Qian, 31Cai Y Qian, 33Chong G Qian, 88Chunhui Qian, 46Di Qian, 36Emily L Qian, 31Feifei Qian, 38Haimeng Qian, 60Holly H Qian, 59

Zhiguo Qian Phones & Addresses

  • 3966 E Beechnut Pl, Chandler, AZ 85249
  • Sun Lakes, AZ
  • San Jose, CA
  • Urbana, IL
  • Champaign, IL
  • Maricopa, AZ

Work

Company: Intel corporation Apr 2010 Address: Chandler, Arizona Position: Sr. analog engineer

Education

Degree: Ph. D School / High School: University of Illinois at Urbana-Champaign 2004 to 2009 Specialities: Electrical and Computer Engineer

Skills

Signal Integrity • Circuit Design • Electromagnetics • Semiconductors • Simulations • Computational Electromagnetics • Algorithms • Eda • Matlab • Spice • Ic • Signal Processing • Modeling • Network Analyzer • High Speed Interfaces

Industries

Semiconductors

Resumes

Resumes

Zhiguo Qian Photo 1

Principal Engineer

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation - Chandler, Arizona since Apr 2010
Sr. Analog Engineer
Apache Design Solutions - San Jose, California May 2009 - Apr 2010
Principal Engineer
University of Illinois at Urbana-Champaign - Urbana-Champaign, Illinois Area Aug 2004 - Apr 2009
Research Assistant
Mentor Graphics - Grenoble Area, France May 2006 - Aug 2006
Summer Intern
Education:
University of Illinois at Urbana-Champaign 2004 - 2009
Ph. D, Electrical and Computer Engineer Southeast University 1997 - 2004
BS & MS, Electrical Engineering
Skills:
Signal Integrity
Circuit Design
Electromagnetics
Semiconductors
Simulations
Computational Electromagnetics
Algorithms
Eda
Matlab
Spice
Ic
Signal Processing
Modeling
Network Analyzer
High Speed Interfaces

Business Records

Name / Title
Company / Classification
Phones & Addresses
Zhiguo Qian
Vice-president
ARIZONA CHINESE AMERICAN HI-TECH ASSOCIATION
1900 W Carla Vis STE 8196, Chandler, AZ 85246
PO Box 8196, Chandler, AZ 85246

Publications

Us Patents

Routing Design For High Speed Input/Output Links

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US Patent:
20140071646, Mar 13, 2014
Filed:
Sep 11, 2012
Appl. No.:
13/610663
Inventors:
Zhiguo Qian - Chandler AZ, US
Kemal Aygun - Chandler AZ, US
International Classification:
H05K 1/02
H05K 3/46
US Classification:
361777, 174250, 174261, 29846
Abstract:
Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.

Bridge Interconnect With Air Gap In Package Assembly

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US Patent:
20140070380, Mar 13, 2014
Filed:
Sep 11, 2012
Appl. No.:
13/610780
Inventors:
Chia-Pin Chiu - Tempe AZ, US
Zhiguo Qian - Chandler AZ, US
Mathew J. Manusharow - Phoenix AZ, US
International Classification:
H01L 23/495
H01L 21/60
US Classification:
257666, 438107, 257E21506, 257E23052
Abstract:
Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Dielectric-Filled Trench Isolation Of Vias

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US Patent:
20220270974, Aug 25, 2022
Filed:
Mar 1, 2022
Appl. No.:
17/684163
Inventors:
- SANTA CLARA CA, US
Zhiguo Qian - Chandler AZ, US
Jianyong Xie - Chandler AZ, US
Assignee:
INTEL CORPORATION - SANTA CLARA CA
International Classification:
H01L 23/538
H01L 21/762
H01L 21/765
H01L 25/065
H01L 29/06
Abstract:
An apparatus is provided which comprises: a substrate, the substrate comprising crystalline material, a first set of one or more contacts on a first substrate surface, a second set of one or more contacts on a second substrate surface, the second substrate surface opposite the first substrate surface, a first via through the substrate coupled with a first one of the first set of contacts and with a first one of the second set of contacts; a second via through the substrate coupled with a second one of the first set of contacts and with a second one of the second set of contacts, a trench in the substrate from the first substrate surface toward the second substrate surface, wherein the trench is apart from, and between, the first via and the second via, and dielectric material filling the trench. Other embodiments are also disclosed and claimed.

Clock Phase Management For Die-To-Die (D2D) Interconnect

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US Patent:
20220271912, Aug 25, 2022
Filed:
May 12, 2022
Appl. No.:
17/743085
Inventors:
Gerald Pasdast - San Jose CA, US
Peipei Wang - San Jose CA, US
Lakshmipriya Seshan - Sunnyvale CA, US
Juan Zeng - San Jose CA, US
Zuoguo Wu - San Jose CA, US
Zhiguo Qian - Chandler AZ, US
Narasimha Lanka - Dublin CA, US
Debendra Das Sharma - Saratoga CA, US
Swadesh Choudhary - Mountain View CA, US
International Classification:
H04L 7/00
Abstract:
Embodiments herein may relate to a die for use in a multi-die package. The die may include clock circuitry that is able to identify a phase of a data signal to be transmitted and a phase of a clock signal to be transmitted on a die-to-die (D2D) link. The clock circuitry may further be configured adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal such that the clock signal and the data signal are received by a receiver die of the D2D link with a 90 degree phase difference. Other embodiments may be described and claimed.

Shield Structures In Microelectronic Assemblies Having Direct Bonding

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US Patent:
20220199546, Jun 23, 2022
Filed:
Dec 18, 2020
Appl. No.:
17/127382
Inventors:
- Santa Clara CA, US
Gerald S. Pasdast - San Jose CA, US
Kimin Jun - Portland OR, US
Zhiguo Qian - Chandler AZ, US
Johanna M. Swan - Scottsdale AZ, US
Aleksandar Aleksov - Chandler AZ, US
Shawna M. Liff - Scottsdale AZ, US
Mohammad Enamul Kabir - Portland OR, US
Feras Eid - Chandler AZ, US
Kevin P. O'Brien - Portland OR, US
Han Wui Then - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/552
H01L 25/065
H01L 23/00
H01L 23/498
H01L 23/66
Abstract:
Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.

Glass Substrates Having Signal Shielding For Use With Semiconductor Packages And Related Methods

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US Patent:
20230103183, Mar 30, 2023
Filed:
Sep 24, 2021
Appl. No.:
17/485045
Inventors:
- Santa Clara CA, US
Srinivas V. Pietambaram - Chandler AZ, US
Kemal Aygun - Tempe AZ, US
Telesphor Kamgaing - Chandler AZ, US
Zhiguo Qian - Chandler AZ, US
Jiwei Sun - Chandler AZ, US
International Classification:
H01L 23/552
H01L 23/498
H01L 21/48
Abstract:
Glass substrates having signal shielding for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a core layer defining a channel and a TGV. The channel at least partially surrounding the TGV. A signal transmission line is provided in the opening and extending through the core layer. An electrically conductive material positioned in the channel. The conductive material to provide electromagnetic shielding to the transmission line.

Embedded Glass Cores In Package Substrates And Related Methods

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US Patent:
20230088928, Mar 23, 2023
Filed:
Sep 23, 2021
Appl. No.:
17/483444
Inventors:
- Santa Clara CA, US
Jiwei Sun - Chandler AZ, US
Zhiguo Qian - Chandler AZ, US
Srinivas Pietambaram - Chandler AZ, US
International Classification:
H01L 23/498
H01L 23/15
H01L 49/02
H01L 21/48
Abstract:
Embedded glass cores in package substrates and related methods are disclosed herein including an integrated circuit including a substrate having a first side and a second side opposite the first side, a plurality of vias disposed within the substrate to electrically couple corresponding contacts on the first and second sides of the substrate, a glass core surrounding a first via of the plurality of vias, and an organic core surrounding a second via of the plurality of vias, the second via different than the first via.

Airgap Structures For High Speed Signal Integrity

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US Patent:
20210375746, Dec 2, 2021
Filed:
May 27, 2020
Appl. No.:
16/884452
Inventors:
- Santa Clara CA, US
Jeremy Ecton - Gilbert AZ, US
Aleksandar Aleksov - Chandler AZ, US
Haobo Chen - Chandler AZ, US
Xiaoying Guo - Chandler AZ, US
Brandon C. Marin - Gilbert AZ, US
Zhiguo Qian - Chandler AZ, US
Daryl Purcell - Chandler AZ, US
Leonel Arana - Phoenix AZ, US
Matthew Tingey - Mesa AZ, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 23/522
H01L 23/66
Abstract:
Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.
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Zhiguo Qian from Chandler, AZ, age ~46 Get Report