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Zahi M Kurzum

from Poughkeepsie, NY
Age ~62
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Also known as:
Zahi Manwel Kurzo, Zahi M Kurzo, Azahi Kurzum, Zahi Mannel Kurzun, Zahi Manwel M, Zahi M
Phone and address:
33 Fair Way, Poughkeepsie, NY 12603
(845) 462-1449
Related to:
Rareem Z KurzumArij F Kurzum, 55Raneem Kurzum, 30
Connected to:
Andrea Kurzweil, 29Kenneth Kurzweil, 76Justin M Kurzyna, 49David J Kurzynski, 45Leonard S Kurzynski, 80Cem Kus, 61Christine M Kus, 42Paul R Kus, 54Stanley J Kus, 41Algerd Kusa, 99

Zahi Kurzum Phones & Addresses

  • 33 Fair Way, Poughkeepsie, NY 12603 (845) 462-1449
  • Clemson, SC
  • Sunnyvale, CA
  • Taylors, SC
  • Marlton, NJ
  • 33 Fair Way, Poughkeepsie, NY 12603

Work

Company: Ibm Jan 2005 to Oct 2011 Position: Functional manager and engineer

Education

Degree: Master of Science, Masters School / High School: Clemson University 1987 to 1989 Specialities: Computer Engineering

Skills

Asic • Eda • Physical Design • Software Development • Debugging • Perl • C • Microprocessors • Linux • Algorithms • Vlsi • Integration • Testing • C++ • Unix • Timing Closure • Tcl • Hardware Architecture • Verilog • Software Engineering • Hardware • Embedded Systems • Static Timing Analysis • Computer Architecture • Semiconductors • Cmos • Soc • Microsoft Office • Logic Design • Shell Scripting • Management • Logic Synthesis • Agile Methodologies • Processors • Career Counseling • Coaching • People Management • Html • Rpm • Project Management • Agile Project Management • Change Management • Recruiting • Performance Management • Emotional Intelligence • Team Leadership • Team Building • Windows • Career Development Coaching • Social Media

Languages

English • Arabic • Hebrew

Ranks

Certificate: Ibm Certified Manager

Industries

Information Technology And Services

Resumes

Resumes

Zahi Kurzum Photo 1

Zahi Kurzum

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Location:
New York, NY
Industry:
Information Technology And Services
Work:
Ibm Jan 2005 - Oct 2011
Functional Manager and Engineer
Texas Instruments Jan 1985 - Dec 1986
System and Equipment Test Engineer
Education:
Clemson University 1987 - 1989
Master of Science, Masters, Computer Engineering Clemson University 1982 - 1984
Bachelors, Bachelor of Science, Computer Engineering Carmelite School
Skills:
Asic
Eda
Physical Design
Software Development
Debugging
Perl
C
Microprocessors
Linux
Algorithms
Vlsi
Integration
Testing
C++
Unix
Timing Closure
Tcl
Hardware Architecture
Verilog
Software Engineering
Hardware
Embedded Systems
Static Timing Analysis
Computer Architecture
Semiconductors
Cmos
Soc
Microsoft Office
Logic Design
Shell Scripting
Management
Logic Synthesis
Agile Methodologies
Processors
Career Counseling
Coaching
People Management
Html
Rpm
Project Management
Agile Project Management
Change Management
Recruiting
Performance Management
Emotional Intelligence
Team Leadership
Team Building
Windows
Career Development Coaching
Social Media
Languages:
English
Arabic
Hebrew
Certifications:
Ibm Certified Manager

Publications

Us Patents

Method For Legalizing The Placement Of Cells In An Integrated Circuit Layout

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US Patent:
7089521, Aug 8, 2006
Filed:
Jan 27, 2004
Appl. No.:
10/766549
Inventors:
Zahi M. Kurzum - Poughkeepsie NY, US
Paul Villarrubia - Austin TX, US
Shyam Ramji - Fishkill NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/45
G06F 17/50
US Classification:
716 10, 716 2, 716 8
Abstract:
A method for resolving overlaps in the cell placement (placement legalization) during the physical design phase of an integrated chip design is described. This problem arises in several contexts within the physical design automation area including global and detailed placement, physical synthesis, and ECO (Engineering Change Order) mode for timing/design closure The method involves capturing a view of a given placement, solving a global two-dimensional area migration model and locally perturbing the cells to resolve the overlaps with minimal changes to the given placement. The method first captures a two-dimensional view of the placement including blockage-space, free-space and the given location of cells by defining physical regions. The desired global area migration across the physical regions of the placement image is determined such that it satisfies area capacity-demand constraints. The method also provides moving the cells between physical regions along previously computed directions of migration to minimize the movement cost.

Congestion Mitigation With Logic Order Preservation

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US Patent:
20030217338, Nov 20, 2003
Filed:
May 17, 2002
Appl. No.:
10/063837
Inventors:
Glenn Holmes - Wappingers Falls NY, US
Zahi Kurzum - Poughkeepsie NY, US
Shyam Ramji - Yorktown Heights NY, US
Haoxing Ren - Wappingers Falls NY, US
Paul Villarrubia - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F017/50
US Classification:
716/002000
Abstract:
A method, computer software, and system for performing congestion mitigation in an IC design while preserving global logic order, comprising the steps of carrying out circuit block placement; measuring the congestion for each circuit block to determine if it exceeds a target value; reallocating area to circuit blocks that exceed said target value of congestion solely from adjacent circuit blocks; and removing overlap.

Method For Successive Placement Based Refinement Of A Generalized Cost Function

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US Patent:
20050166164, Jul 28, 2005
Filed:
Jan 27, 2004
Appl. No.:
10/707942
Inventors:
Haoxing Ren - Austin TX, US
Paul Villarrubia - Austin TX, US
Zahi Kurzum - Poughkeepsie NY, US
Shyam Ramji - Fishkill NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F017/50
US Classification:
716002000, 716001000, 716011000
Abstract:
A generalized method for optimizing the global placement of a VLSI chip across multiple cost metrics, such as total wire length, timing, congestion, and signal integrity is described. The method relies upon a “look ahead” technique, combined with any generic cost function that can be used to set placement directives. These placement directives include net weights and cell spreading. The method of performing the placement involves the iterative reuse of the process of successive partitioning. This iterative reuse establishes the capability of looking ahead to determine what is to happen. Based on the look ahead, it is possible to evaluate the qualities of the placement about to be generated. The method proceeds through the placement from while maintaining the current state of the placement along with the look-ahead state of the placement. Directives are generated and modified in order that the next steps applied to the current state of the placement will cause it to change to achieve an ultimate higher quality final output.
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Zahi M Kurzum from Poughkeepsie, NY, age ~62 Get Report