Zachary M Stum

7595241, Sep 29, 2009

Aug 23, 2006

11/466488

Kevin Sean Matocha - Rexford NY, US
Jody Alan Fronheiser - Selkirk NY, US
Larry Burton Rowland - Scotia NY, US
Jesse Berkley Tucker - Niskayuna NY, US
Stephen Daley Arthur - Glenville NY, US
Zachary Matthew Stum - Niskayuna NY, US

General Electric Company - Niskayuna NY

H01L 21/336

438268, 438269, 438273, 257328, 257329, 257E29257

A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

7691711, Apr 6, 2010

Jan 31, 2008

12/023369

Zachary Matthew Stum - Niskayuna NY, US
Kevin Sean Matocha - Rexford NY, US
Jody Alan Fronheiser - Selkirk NY, US
Ljubisa Dragoljub Stevanovic - Clifton Park NY, US

General Electric Company - Niskayuna NY

H01L 21/336

438268, 438607, 257328, 257E29118, 257E29121, 257E2141

A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.

7781312, Aug 24, 2010

Dec 13, 2006

11/610199

Kevin Sean Matocha - Rexford NY, US
Vinayak Tilak - Schenectady NY, US
Stephen Daley Arthur - Glenville NY, US
Zachary Matthew Stum - Niskayuna NY, US

General Electric Company - Niskayuna NY

H01L 21/20

438478, 438483, 257E21054, 257E21065, 427589

A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.

7807556, Oct 5, 2010

Dec 5, 2006

11/566814

Greg Thomas Dunne - Rexford NY, US
Jesse Berkley Tucker - Schenectady NY, US
Stanislav Ivanovich Soloviev - Albany NY, US
Zachary Matthew Stum - Niskayuna NY, US

General Electric Company - Niskayuna NY

H01L 21/22
H01L 21/38

438558, 257E21468

A method for doping impurities into a device layer includes providing a carbonized dopant layer including one or more dopant impurities over a device layer and heat treating the carbonized dopant layer to thermally diffuse the dopant impurities into the device layer.

7829402, Nov 9, 2010

Feb 10, 2009

12/368498

Kevin Sean Matocha - Rexford NY, US
Stephen Daley Arthur - Glenville NY, US
Ramakrishna Rao - Bangalore, IN
Peter Almern Losee - Rensselaer NY, US
Zachary Matthew Stum - Niskayuna NY, US

General Electric Company - Niskayuna NY

H01L 21/336
H01L 21/8234

438197, 438510, 438514, 257E2117, 257E21051, 257E21058, 257E21227, 257E21247, 257E21248, 257E21421

A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.

8377756, Feb 19, 2013

Jul 26, 2011

13/190723

Stephen Daley Arthur - Glenville NY, US
Kevin Matocha - Starkville MS, US
Peter Sandvik - Niskayuna NY, US
Zachary Stum - Niskayuna NY, US
Peter Losee - Rensselaer NY, US
James McMahon - Clifton Park NY, US

General Electric Company - Niskayuna NY

H01L 29/10
H01L 29/76

438135, 438202, 438220, 438258, 438268, 327424, 327438, 257329, 257334, 257341, 257E2141, 257E21418, 257E2706, 257E29257, 257E29262

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well () (P type) and two parallel sources () (N type) formed within the well. A plurality of source rungs () (doped N) connect sources () at multiple locations. Regions between two rungs () comprise a body () (P type). These features are formed on an N-type epitaxial layer (), which is formed on an N-type substrate (). A contact () extends across and contacts a plurality of source rungs () and bodies (). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

8377812, Feb 19, 2013

Jun 12, 2009

12/483469

Kevin Sean Matocha - Rexford NY, US
Gregory Keith Dudoff - Clifton Park NY, US
William Gregg Hawkins - Rexford NY, US
Zachary Matthew Stum - Niskayuna NY, US
Stephen Daley Arthur - Glenville NY, US
Dale Marius Brown - Niskayuna NY, US

General Electric Company - Niskayuna NY

H01L 21/28

438586, 438655, 438664, 438683, 438931, 257E21063, 257E21165, 257E21182

The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800 C. The gate contact and the source contact comprise a metal silicide.

8507986, Aug 13, 2013

Jan 14, 2013

13/740758

Kevin Sean Matocha - Starkville MS, US
Peter Micah Sandvik - Niskayuana NY, US
Zachary Matthew Stum - Niskayuna NY, US
Peter Almren Losee - Clifton Park NY, US
James Jay McMahon - Clifton Park NY, US

General Electric Company - Niskayuna NY

H01L 29/76
H01L 21/332

257341, 257327, 257329, 257334, 257337, 257342, 257E2141, 257E21418, 257E2706, 257E29262, 257E29257, 438135, 438202, 438220, 438258, 438268

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.