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Yusheng S Lin

from Phoenix, AZ
Age ~55
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Also known as:
Yu Sheng Lin, Yu-Sheng Lin, Sheng Lin Yu, Lin S Yusheng
Phone and address:
4522 E Gold Poppy Way, Phoenix, AZ 85044
(602) 547-2140
Related to:
Nathan LinNan Lin, 67Peng Luo, 54Jennifer Park, 25Lucy L Lin, 61
Connected to:
Aaron E Lin, 63Ai Lin, 70Angela X Lin, 52Antoine W Lin, 46Bennie Lin, 52Bevin Lin, 45Bi Q Lin, 48Bill T Lin, 70Blaise C Lin, 69Botao Lin, 41

Yusheng Lin Phones & Addresses

  • 4522 E Gold Poppy Way, Phoenix, AZ 85044 (602) 547-2140
  • Pocatello, ID
  • 151 Osgood St, Andover, MA 01810 (978) 409-2460
  • North Andover, MA
  • Jamestown, NC
  • Dorchester, MA
  • Lowell, MA
  • Greensboro, NC
  • 39 Royal Crest Dr, North Andover, MA 01845

Work

Position: Production Occupations

Resumes

Resumes

Yusheng Lin Photo 1

Engineering Manager At On Semiconductor

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Location:
Pocatello, Idaho Area
Industry:
Semiconductors
Experience:
ON Semiconductor (Public Company; 10,001 or more employees; Semiconductors industry): Engineering Manager,  (-) 
Yusheng Lin Photo 2

Yusheng Lin

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Business Records

Name / Title
Company / Classification
Phones & Addresses
Yusheng Lin
Director
China Housing & Land Development, Inc

Publications

Us Patents

Low Stress Asymmetric Dual Side Module

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US Patent:
20220415857, Dec 29, 2022
Filed:
Aug 30, 2022
Appl. No.:
17/823149
Inventors:
- Phoenix AZ, US
Atapol PRAJUCKAMOL - Thanyaburi, TH
Stephen ST. GERMAIN - Gilbert AZ, US
Yusheng LIN - Phoenix AZ, US
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ
International Classification:
H01L 25/07
H01L 25/00
H01L 23/367
H01L 23/00
Abstract:
Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Low Stress Asymmetric Dual Side Module

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US Patent:
20220415858, Dec 29, 2022
Filed:
Aug 30, 2022
Appl. No.:
17/823164
Inventors:
- Phoenix AZ, US
Atapol PRAJUCKAMOL - Thanyaburi, TH
Stephen ST. GERMAIN - Gilbert AZ, US
Yusheng LIN - Phoenix AZ, US
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ
International Classification:
H01L 25/07
H01L 25/00
H01L 23/367
H01L 23/00
Abstract:
Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Semiconductor Package Electrical Contact Structures And Related Methods

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US Patent:
20220384204, Dec 1, 2022
Filed:
Jun 23, 2022
Appl. No.:
17/808338
Inventors:
- Phoenix AZ, US
Michael J. SEDDON - Gilbert AZ, US
Yusheng LIN - Phoenix AZ, US
Takashi NOMA - Ota, JP
Eiji KUROSE - Oizumi-machi, JP
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ
International Classification:
H01L 21/3065
H01L 23/00
H01L 23/31
H01L 23/29
H01L 21/56
Abstract:
Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

Die Sidewall Coatings And Related Methods

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US Patent:
20220351977, Nov 3, 2022
Filed:
Jul 19, 2022
Appl. No.:
17/813348
Inventors:
- Phoenix AZ, US
Yusheng LIN - Phoenix AZ, US
Michael J. SEDDON - Gilbert AZ, US
Chee Hiong CHEW - Seremban, MY
Soon Wei WANG - Seremban, MY
Eiji KUROSE - Oizumi-machi, JP
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ
International Classification:
H01L 21/302
H01L 21/56
H01L 23/31
H01L 21/48
H01L 23/00
H01L 21/78
H01L 23/12
Abstract:
Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Power Modules And Related Methods

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US Patent:
20220293499, Sep 15, 2022
Filed:
May 27, 2022
Appl. No.:
17/804423
Inventors:
- Phoenix AZ, US
Asif JAKWANI - Scottsdale AZ, US
Chee Hiong CHEW - Seremban, MY
Yusheng LIN - Phoenix AZ, US
Sravan VANAPARTHY - Scottsdale AZ, US
Silnore Tejero SABANDO - Lapulapu City, PH
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ
International Classification:
H01L 23/495
H01L 21/48
H01L 23/31
Abstract:
Implementations of power modules may include: a substrate having a first side and a second side. The power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate. The power module may also include an opening extending from a first side of the substrate to an outer edge of the molding compound. The opening may be configured to receive a coupling device and the coupling device may be configured to couple with a heat sink or a package support.

Fan-Out Wafer Level Packaging Of Semiconductor Devices

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US Patent:
20220285267, Sep 8, 2022
Filed:
Mar 2, 2021
Appl. No.:
17/249436
Inventors:
- Phoenix AZ, US
Yusheng LIN - Phoenix AZ, US
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ
International Classification:
H01L 23/522
H01L 23/31
H01L 25/065
H01L 23/538
H01L 23/00
Abstract:
In a general aspect, a semiconductor device assembly can include a semiconductor die having a back side and a front side, the back side being coupled with a base, the front side including active circuitry. The assembly can include a first resin encapsulation layer disposed on a first portion of the front side. The first resin encapsulation layer can be patterned to define a first opening exposing a second portion of the front side through the first resin encapsulation layer. The assembly can include a signal distribution structure that is disposed on the first resin encapsulation layer, and electrically coupled with the front side through the first opening. The assembly can include a second resin encapsulation layer disposed on a first portion of the signal distribution structure, the second resin encapsulation layer being patterned to define a second opening that exposes a second portion of the signal distribution structure.

Reinforced Semiconductor Die And Related Methods

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US Patent:
20220254734, Aug 11, 2022
Filed:
Apr 27, 2022
Appl. No.:
17/660941
Inventors:
- Phoenix AZ, US
Erik Nino TOLENTINO - Seremban, MY
Yusheng LIN - Phoenix AZ, US
Swee Har KHOR - Kuala Lumpur, MY
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ
International Classification:
H01L 23/00
H01L 23/495
H01L 21/78
H01L 21/48
Abstract:
Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.

Spacer With Pattern Layout For Dual Side Cooling Power Module

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US Patent:
20220208635, Jun 30, 2022
Filed:
Dec 29, 2020
Appl. No.:
17/136286
Inventors:
- Phoenix AZ, US
Liangbiao CHEN - Scarborough ME, US
Yusheng LIN - Phoenix AZ, US
Chee Hiong CHEW - Seremban, MY
Assignee:
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC - Phoenix AZ
International Classification:
H01L 23/367
H01L 23/373
H01L 21/48
Abstract:
A method includes bonding a device die to a direct bonded metal (DBM) substrate, bonding a spacer block to the device die, and at least partially reducing coefficient of thermal expansion (CTE) mismatches between the DBM substrate, the spacer block and the device die. At least partially reducing the CTE mismatches between the DBM substrate, the spacer block and the device die includes at least one of: disposing an arrangement of pillars and grooves in a surface region of the spacer block coupled to the device die, disposing at least one cavity in the spacer block, and disposing a groove in an outer conductive layer of the DBM substrate.
Control profile
Yusheng S Lin from Phoenix, AZ, age ~55 Get Report