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Yongsik Youn

from Cupertino, CA
Age ~56
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Also known as:
Yong Sik Youn
Related to:
Yong-Sik YounYong S Youn, 58
Connected to:
Chung H Youn, 97Dong Y Youn, 42Erik J Youn, 42Hannah Youn, 33Hwa S Youn, 54Joanne C Youn, 50Michael J Youn, 43Seong W Youn, 52Su J Youn, 43Youn S Youn, 40

Yongsik Youn Phones & Addresses

  • Cupertino, CA
  • San Diego, CA
  • 19400 Sorenson Ave APT 129, Cupertino, CA 95014

Work

Company: Sequoia communications Apr 2008 Position: Rf/analog ic designer

Education

Degree: Ph. D School / High School: Korea Advanced Institute of Science and Technology 2001 to 2008 Specialities: Electrical and Electronic Engineering

Skills

Design • Analog • Research • Power • Rf • Wireless • Manufacturing • Pll • Electronic Engineering • Communications • Circuit Design • Ic

Industries

Semiconductors

Resumes

Resumes

Yongsik Youn Photo 1

Rf And Analog Power Ic Design Engineer And Et-Smic Leader

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Sequoia Communications since Apr 2008
RF/Analog IC designer
Entropic Communications Mar 2004 - Mar 2008
RF/Analog IC designer
Electronics and Telecommunications Research Institute (ETRI) Sep 1998 - Sep 2003
RF/Analog IC Designer
Education:
Korea Advanced Institute of Science and Technology 2001 - 2008
Ph. D, Electrical and Electronic Engineering
Skills:
Design
Analog
Research
Power
Rf
Wireless
Manufacturing
Pll
Electronic Engineering
Communications
Circuit Design
Ic

Publications

Us Patents

Tracking Filter For Tuner

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US Patent:
20060154636, Jul 13, 2006
Filed:
Dec 14, 2005
Appl. No.:
11/302876
Inventors:
Peter Shah - San Diego CA, US
YongSik Youn - San Diego CA, US
Martin Alderton - San Diego CA, US
International Classification:
H04B 1/18
US Classification:
455290000
Abstract:
A tuner uses a bank of tracking filters to preselect a channel to be received. Each tracking filter covers a range of frequencies. The tracking filters are tunable in frequency using switched capacitors and are tunable in gain by using switched resistors. The switched resistors can be controlled by an automatic gain control circuit that monitors the selected signal and adjust the tracking filter gain to achieve a desired signal level. A switch directs the received signal or signal from a test tone generator into the tracking filters. The test tone, generated by a frequency agile circuit, can be used to calibrate the filters, both in frequency and gain.

Sense Amplifier Circuitry For Resistive Type Memory

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US Patent:
20130322154, Dec 5, 2013
Filed:
Jun 4, 2012
Appl. No.:
13/488432
Inventors:
YongSik Youn - Cupertino CA, US
Adrian E. Ong - Pleasanton CA, US
SOOHO CHA - Seoul, KR
Chan-kyung Kim - Hwaseong-si, KR
International Classification:
G11C 7/06
G11C 7/12
G11C 11/00
US Classification:
365148
Abstract:
Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

Sense Amplifier Circuitry For Resistive Type Memory

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US Patent:
20140003124, Jan 2, 2014
Filed:
Jun 29, 2012
Appl. No.:
13/538869
Inventors:
YongSik Youn - Cupertino CA, US
Sooho CHA - Seoul, KR
Chan-kyung Kim - Hwaseong-si, KR
International Classification:
G11C 7/06
US Classification:
365148
Abstract:
Example embodiments include a resistive type memory sense amplifier circuit including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is re-used during at least a “set” or “amplification” stage of the sense amplifier circuit, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is caused to swing in response to a delta average current between a reference line current and a bit line current. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit. Also disclosed is a current mirror circuit, which can be used in conjunction with the disclosed sense amplifier circuit. In yet another embodiment, a sense amplifier circuit includes the capability of read/re-write operation.

Enhanced Temperature Range For Resistive Type Memory Circuits With Pre-Heat Operation

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US Patent:
20150043266, Feb 12, 2015
Filed:
Nov 27, 2013
Appl. No.:
14/092867
Inventors:
- Suwon-si, KR
YongSik YOUN - Cupertino CA, US
Assignee:
Samsung Electronics Co., Ltd. - Suwon-si
International Classification:
G11C 29/56
G11C 13/00
US Classification:
365148
Abstract:
Example embodiments include devices, systems, and methods for enhancing an operating temperature range for resistive type memory devices. After powering up the resistive type memory die, the die temperature of the resistive type memory die is sensed. If the sensed die temperature is less than a predefined temperature threshold, one or more heaters proximately disposed to one or more memory cells of the resistive type memory die are enabled. The heaters are disabled responsive to the sensed die temperature being greater than a predefined temperature threshold. Memory write operations are enabled responsive to the sensed die temperature being greater than the predefined temperature threshold. After enabling the memory write operations, an enabled state of the memory write operations is maintained until the resistive type memory die is powered down. If the die temperature happens to fall below the predefined temperature threshold at a later time, additional heat is produced.

Write Driver In Sense Amplifier For Resistive Type Memory

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US Patent:
20140112053, Apr 24, 2014
Filed:
Oct 24, 2012
Appl. No.:
13/659882
Inventors:
YongSik Youn - Cupertino CA, US
SOOHO CHA - Seoul, KR
DongSeok Kang - hwasung-si, KR
Chan-kyung Kim - Hwaseong-si, KR
International Classification:
G11C 7/06
US Classification:
365148
Abstract:
Example embodiments include a level shifting write driver in a sense amplifier for a resistive type memory. The write driver may include a cross-coupled latch circuit, a first output section, a second output section, and an input section. The first output section includes one or more first driving transistors to drive a first current through the first output section and not through the cross-coupled latch. The second output section includes one or more second driving transistors configured to drive a second current through the second output section and not through the cross-coupled latch. The current flows of the outputs sections are isolated from the latch circuit. In some embodiments, no two PMOS type transistors are serially connected, thereby reducing the consumption of die area. In some embodiments, a single control signal is used to operate the write driver.
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Yongsik Youn from Cupertino, CA, age ~56 Get Report