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Yogesh K Ramadass

from San Jose, CA
Age ~41
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Connected to:
Elizabeth S Ramadass, 82Sivakumar Ramadas, 58Angus A Ramadeen, 76David J Ramadei, 37Laura M Ramadei, 40Darcy E Ramadge, 49Fuad Y Ramadhan, 32Niles D Ramadhin, 36Arvind K Ramadorai, 59Chithra Ramadoss, 47

Yogesh Ramadass Phones & Addresses

  • 2468 Redbud Ct, San Jose, CA 95128
  • Dallas, TX
  • Melbourne, FL
  • Cambridge, MA

Work

Company: Ieee solid-state circuits society Jan 2019 Position: Distinguished lecturer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Massachusetts Institute of Technology 2004 to 2006 Specialities: Electrical Engineering

Skills

Mixed Signal • Cmos • Power Management • Analog • Ic • Low Power Design • Dc Dc • Analog Circuit Design • Embedded Systems • Energy Harvesting • Circuit Design • Spectre • Integrated Circuit Design • Integrated Circuits

Industries

Semiconductors

Resumes

Resumes

Yogesh Ramadass Photo 1

Director

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Ieee Solid-State Circuits Society
Distinguished Lecturer
Ieee Symposium on Vlsi Circuits Jun 2016 - Dec 2018
Member of Technical Program Committee
Ieee Journal of Solid-State Circuits 2014 - 2015
Associate Editor
Ieee Islped 2012 - 2014
Sub-Committee Chair
Ieee International Solid-State Circuits Conference 2012 - 2014
Chair - Power Management Sub-Committee
Education:
Massachusetts Institute of Technology 2004 - 2006
Doctorates, Doctor of Philosophy, Electrical Engineering Indian Institute of Technology, Kharagpur 2000 - 2004
Skills:
Mixed Signal
Cmos
Power Management
Analog
Ic
Low Power Design
Dc Dc
Analog Circuit Design
Embedded Systems
Energy Harvesting
Circuit Design
Spectre
Integrated Circuit Design
Integrated Circuits

Publications

Us Patents

Circuit And Method To Improve Energy Harvesting Efficiency In Piezoelectric Harvesters

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US Patent:
8026650, Sep 27, 2011
Filed:
Sep 14, 2009
Appl. No.:
12/558820
Inventors:
Yogesh Ramadass - Cambridge MA, US
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
H01L 41/113
US Classification:
310318, 310319
Abstract:
An energy harvester circuit is provided. The energy harvester circuit includes a harvesting module for extracting energy from an ambient source. A bias flip module manages the manner in which voltage across the harvesting module transitions when input current from the harvesting module changes direction so as to allow a majority of the charge available from the harvesting module to be extracted. A voltage transitioning module is shared amongst one or more DC-DC converters for efficient energy management.

Circuit And Method To Startup From Very Low Voltages And Improve Energy Harvesting Efficiency In Thermoelectric Harvesters

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US Patent:
8305050, Nov 6, 2012
Filed:
Oct 12, 2009
Appl. No.:
12/577421
Inventors:
Yogesh Ramadass - Cambridge MA, US
Anantha Chandrakasan - Belmont MA, US
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
G05F 1/00
G05F 3/00
H02J 1/00
H02J 1/16
H02J 3/00
H02J 3/30
US Classification:
323204
Abstract:
An energy harvesting system is provided that includes a startup module for starting the energy harvesting system operation from a completely OFF state. The startup module uses mechanical vibrations due to motion to trigger a switch which permits the startup module to charge one or more first capacitive elements so to as reach a first defined voltage. A storage module buffers energy obtained from a thermoelectric harvester to be used by a load device. The storage module commences storing energy from the thermoelectric harvester when the first defined voltage has been reached allowing charging of one or more second capacitive elements to reach a second defined voltage. A DC-DC converter module provides regulated voltage to the load device after energy has been transferred from the thermoelectric harvester. The DC-DC converter module determines whether the second defined voltage has been reached and releases stored energy in the one or more first capacitive elements and the load device.

Circuit And Method For A Fully Integrated Switched-Capacitor Step-Down Power Converter

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US Patent:
20090072800, Mar 19, 2009
Filed:
Dec 31, 2007
Appl. No.:
11/967714
Inventors:
Yogesh K. Ramadass - Cambridge MA, US
Ayman A. Fayed - Wylie TX, US
Baher Haroun - Allen TX, US
International Classification:
G05F 1/10
G05F 1/00
US Classification:
323271, 323284
Abstract:
A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a digitally controlled transfer capacitor. A pair of non-overlapping, fixed frequency clock signals is provided to a switched capacitor circuit including the switched capacitor matrix and a load capacitor coupled to the output terminal. A DC input voltage supply is provided. A hysteretic feedback loop is used to control the voltage at the output as a stepped-down voltage from the input by digitally modulating the transfer capacitor using switches in the switch matrix to couple more, or fewer, transfer capacitors to the output terminal during a clock cycle. A coarse and a fine adjustment circuit are provided to improve the regulation during rapid changes in load power. A method of operating the regulator is disclosed.

Hysteretic Charger For Energy Harvester Devices

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US Patent:
20130043857, Feb 21, 2013
Filed:
Aug 15, 2012
Appl. No.:
13/586531
Inventors:
Yogesh K. Ramadass - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G05F 3/02
US Classification:
323311
Abstract:
A hysteretic converter includes an inductor coupled between a source of voltage and a switch node. A low side switch is coupled between the switch node and a reference voltage. A high side switch is coupled between the switch node and the output of the converter. A driver controls the low side and high side switches, wherein the low side switch is turned on until the input current rises to a predetermined set point, the predetermined setpoint can be adapted to input current from the source of voltage.

Maximum Power Point Tracking Circuit Generic To A Variety Of Energy Harvester Devices

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US Patent:
20130043858, Feb 21, 2013
Filed:
Aug 15, 2012
Appl. No.:
13/586557
Inventors:
Yogesh K. Ramadass - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G05F 3/02
US Classification:
323311
Abstract:
A maximum power point tracking circuit for an energy harvester device, the tracking circuit requiring nanoampere current in a standby mode, includes a maximum power point circuits utilizing a predetermined fraction of the open circuit input voltage to determine the maximum power point for energy harvester device. A circuit determines the predetermined fraction of the open circuit voltage of the energy harvester device. A sample and hold circuit measures and holds him the predetermined fraction of the open circuit voltage of the energy harvester device for use by the maximum power point circuit

Piezoelectric Device

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US Patent:
20140062256, Mar 6, 2014
Filed:
Aug 30, 2013
Appl. No.:
14/015647
Inventors:
Yogesh Kumar Ramadass - Dallas TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H02N 2/18
US Classification:
310319
Abstract:
Piezoelectric harvesting devices are disclosed herein. An embodiment of a harvesting device includes a cantilever having a resonant frequency associated therewith, wherein the cantilever vibrates when in the presence of a vibration source, and wherein the harvesting device generates a current upon vibration of the cantilever. The generated current is present at an output. A bias flip circuit is used to tune the resonant frequency of the harvesting device based on measurements of the vibration source that causes the cantilever to vibrate, wherein the bias flip circuit includes a switch that connects and disconnects an inductor to the output.

Integration Of A Passive Component In A Cavity Of An Integrated Circuit Package

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US Patent:
20220415768, Dec 29, 2022
Filed:
Aug 30, 2022
Appl. No.:
17/898656
Inventors:
- Dallas TX, US
Rajeev Dinkar JOSHI - Cupertino CA, US
Sreenivasan K. KODURI - Allen TX, US
Sujan Kundapur MANOHAR - Dallas TX, US
Yogesh K. RAMADASS - San Jose CA, US
Anindya PODDAR - Sunnyvale CA, US
International Classification:
H01L 23/495
H01L 23/498
H01L 23/00
H01L 21/48
Abstract:
A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

Process For Thin Film Capacitor Integration

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US Patent:
20220375836, Nov 24, 2022
Filed:
May 19, 2021
Appl. No.:
17/325197
Inventors:
- Dallas TX, US
Yogesh Kumar Ramadass - San Jose CA, US
Salvatore Frank Pavone - Murphy TX, US
Mahmud Halim Chowdhury - Richardson TX, US
International Classification:
H01L 23/495
H01L 23/00
Abstract:
Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.
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Yogesh K Ramadass from San Jose, CA, age ~41 Get Report