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Ygal Te Arbel

from Morgan Hill, CA
Age ~69
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Related to:
Nurit ArbelLaine K Tengan, 58Nurit Bar, 64Anna M Arbel, 61Barbara Szewieczek, 98
Connected to:
Elinor Arbel, 49Emanuel R Arbel, 94Naomi Arbel, 54Sara Arbel, 82Alex Arbelaez, 39Alexandra Arbelaez, 43Erika A Arbelaez, 34Gustavo G Arbelaez, 62Jennifer H Arbelaez, 45Juan C Arbelaez, 57

Ygal Arbel Phones & Addresses

  • 16870 Malbec Dr, Morgan Hill, CA 95037 (650) 766-4546
  • Palo Alto, CA
  • San Jose, CA
  • Belmont, CA
  • Atherton, CA
  • Los Altos, CA
  • Milpitas, CA
  • Austin, TX
  • Santa Clara, CA

Resumes

Resumes

Ygal Arbel Photo 1

Distinguished Engineer

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Location:
16870 Malbec Dr, Morgan Hill, CA 95037
Industry:
Semiconductors
Work:
Xilinx since Apr 2010
Principal Architect
Anchor Bay Technologies Inc Aug 2006 - Apr 2010
ASIC SoC Architect
Metta Technology Inc May 2005 - Jul 2006
Chief Architec, SoC
Parama Networks Mar 2000 - Apr 2005
Director VLSI Architecture
Tripath 1998 - 2000
Principal DSP Engineer
Education:
Stanford 1984 - 1985
Technion 1977 - 1981
Ironi Tet 1969 - 1973
Metsada
Skills:
Soc
Digital Signal Processors
Asic
Verilog
Microprocessors
Vlsi
Fpga
Embedded Systems
Rtl Design
Systemverilog
Hardware Architecture
Functional Verification
Ygal Arbel Photo 2

Ygal Arbel

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Publications

Us Patents

Hitless Reconfiguration Of A Switching Network

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US Patent:
7139291, Nov 21, 2006
Filed:
Apr 4, 2002
Appl. No.:
10/116664
Inventors:
Ygal Arbel - Belmont CA, US
Robert Louis Caulk - Livermore CA, US
Assignee:
Bay Microsystems, Inc. - San Jose CA
International Classification:
H04J 3/02
H04L 12/28
H04L 12/56
H04L 12/66
US Classification:
370537, 370422, 370539
Abstract:
A multi-stage switching network that can hitlessly reconfigure itself comprising a controller that controls each stage separately. The controller designates the paths through each stage according to the set of paths currently active. If the set of paths changes, the controller sends a new set of paths to the first stage while using the old set of paths for the second stage during a first frame. On the next frame, the controller causes both stages to use the new set of paths.

System And Method For Decoding Audio/Video Data Such As Dvd Or/And Dvb Data

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US Patent:
7184450, Feb 27, 2007
Filed:
Apr 28, 1999
Appl. No.:
09/301438
Inventors:
Christopher K. Wolf - San Jose CA, US
Ygal Arbel - Belmont CA, US
Himanshu A. Sanghavi - Fremont CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H04J 3/04
H04L 12/28
H04N 5/91
H04N 5/262
US Classification:
370535, 370412, 386 98, 3484231
Abstract:
A system () for decoding a data stream allocated into data packets contains a control unit (), a stream demultiplexer (), audio and video decoders ( and ), a memory management unit (), and audio and video input and output buffers. Upon demultiplexing and depacketizing the data packets without interrupting the control unit, the demultiplexer sends encoded audio and video data to the audio and video input buffers. Video messages dealing with video timing information and identifying where encoded video data is stored in the video input buffer are furnished by the demultiplexer for use by the control unit. Utilizing corresponding video instructions provided from the control unit, the video decoder decodes encoded video data to produce decoded video data supplied to the video output buffer. The audio decoder decodes encoded audio data to produce decoded audio data supplied to the audio output buffer. The memory management unit controls transfer of decoded audio data to and from the audio output buffer.

Switching Network

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US Patent:
7184662, Feb 27, 2007
Filed:
Oct 10, 2001
Appl. No.:
09/974448
Inventors:
Ygal Arbel - Belmont CA, US
Robert Louis Caulk - Livermore CA, US
Assignee:
Bay Microsysems, Inc. - San Jose CA
International Classification:
H04J 14/00
US Classification:
398 56, 398 45, 370372
Abstract:
A two-stage switching network that takes data from an input and first switches it through a space stage into a buffer. Data from the buffer is then switched in a time-space stage to an output. Each buffer, advantageously, holds one frame of data. Further, there are two buffers such that one may be filled from the input while the other is emptied to the output, and vice-versa. A maximum amount of data may be switched in space and time regardless of its origin and destination, effecting a switching network that is capable of the widest SONET-specified bandwidth.

Fractional Phase-Locked Loop For Generating High-Definition And Standard-Definition Reference Clocks

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US Patent:
7852408, Dec 14, 2010
Filed:
May 16, 2006
Appl. No.:
11/383551
Inventors:
Ygal Arbel - Morgan Hill CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H04N 5/06
H04N 5/46
H04N 9/45
H04N 9/455
H03L 7/85
H03L 7/89
H03L 7/06
H03L 7/26
H03B 1/00
US Classification:
348521, 348555, 348558, 331 1 A, 331 16, 331 34, 331 74, 327156
Abstract:
A programmable fractional phase-locked loop for generating a 148. 50000 MHz high-definition television reference clock and a 148. 35164 MHz high-definition reference clock from a 27 MHz crystal is disclosed. To generate the 148. 50000 MHz reference clock, the fractional phase-locked loop is multiplied by 11/2, and to generate the 148. 35164 MHz reference clock, the fractional phase-locked loop is multiplied by 500/91. Inside the fractional-phase locked loop however, the fraction 11/2 is represented by a denominator that is an integral power of 2, and the fraction 500/91 is represented by a denominator that is an integral multiple of 91.

Overhead Processing In Telecommunications Nodes

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US Patent:
20040008673, Jan 15, 2004
Filed:
Jul 11, 2002
Appl. No.:
10/193580
Inventors:
Ygal Arbel - Belmont CA, US
Peter Joseph Giacomini - South Plainfield NJ, US
International Classification:
H04L012/50
US Classification:
370/360000
Abstract:
A novel telecommunications node architecture is disclosed that comprises a novel technique for overhead processing. Some embodiments of the present invention advantageously exhibit a smaller footprint, reduced cost, and lower power consumption than some architectures in the prior art. The illustrative embodiment comprises a plurality of input processors, a switch, an overhead processor, and a plurality of output processors.

Compact And Hitlessly-Resizable Multi-Channel Queue

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US Patent:
20060230052, Oct 12, 2006
Filed:
Apr 12, 2005
Appl. No.:
11/103978
Inventors:
Ygal Arbel - Morgan Hill CA, US
Assignee:
Parama Networks, Inc. - Santa Clara CA
International Classification:
G06F 7/00
US Classification:
707101000
Abstract:
A queue is disclosed (i) that provides for single-channel and multi-channel operation and that can change between single-channel and multi-channel operation during operation hitlessly, (ii) in which the number of channels and each channel's size can be changed during operation hitlessly, and (iii) is compact. To accomplish this, the illustrative embodiment comprises a group of doubly-linked lists, one for each channel's storage. One set of links indicates the node where the next datum is to be written and the other set of links indicates the node where the next datum is to be read. By bifurcating each channel's queue into a set of write links and read links, the illustrative embodiment can resize a channel during operation hitlessly.

Method And Apparatus For Handling Incoming Telephone Calls

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US Patent:
52767310, Jan 4, 1994
Filed:
Apr 26, 1991
Appl. No.:
7/692081
Inventors:
Ygal Arbel - Sunnyvale CA
Timothy L. Wilson - Austin TX
Gordon Ford - Round Rock TX
Cathy Arledge - Austin TX
Tracy L. Rust - Austin TX
Assignee:
ROLM Company - Santa Clara CA
International Classification:
H04M 166
H04M 342
H04M 1100
US Classification:
379 88
Abstract:
Method and apparatus for handling incoming telephone calls and, in particular: (a) for delivering predetermined messages to predetermined calling parties; (b) predetermined, prioritorized screening of incoming telephone calls; and (c) for re-routing incoming telephone calls on the basis of predetermined selection criteria. The predetermined selection criteria include information such as the calling parties, call origination information, call origination information with wildcards, time, date, or a combination of these factors. Call origination information includes, but is not limited to, Automatic Number Identification ("ANI"), private network tie line identification, trunk ID, Wide Area Telephone Service ("WATS"), and extension numbers.

Method And Apparatus For Computing Mpeg Video Reconstructed Dct Coefficients

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US Patent:
59829354, Nov 9, 1999
Filed:
Apr 11, 1997
Appl. No.:
8/834059
Inventors:
Ygal Arbel - Belmont CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06K 936
G06K 946
H04N 1415
US Classification:
382233
Abstract:
A novel apparatus and method is disclosed to perform discrete cosine transform (DCT) coefficient reconstruction more efficiently and using less hardware resources than prior art techniques. The invention comprises a correction factor generator apparatus which computes a correction factor which is used in the DCT coefficient reconstruction process. Use of the correction factor enables DCT coefficient reconstruction to be performed using lesser computations and lesser hardware resources than prior art techniques. The apparatus and method can be used to perform DCT coefficient reconstruction for both MPEG-1 and MPEG-2 encoded video data streams.
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Ygal Te Arbel from Morgan Hill, CA, age ~69 Get Report