Iwen Te Yao

6845482, Jan 18, 2005

May 10, 2001

09/853332

Iwen Yao - San Diego CA, US

Qualcomm Incorporated - San Diego CA

H03M 1300

714755

Techniques to efficiently generate memory addresses for a Turbo code interleaver using a number of look-up tables. An interleaver includes a storage unit, sets of tables, and an address generator. The storage unit stores K elements for a data packet at locations representative of an R×C array, with the elements being stored in a first (e. g. , linear) order and provided in a second (e. g. , interleaved) order. A first set of table(s) stores sequences (e. g. , inter-row permutation sequences P, P, P, and P) used to perform row permutation of the array to map from the first order to the second order. A second set of table(s) stores sequences (e. g. , intra-row base sequences and prime number sequences) used to perform column permutation. The address generator receives a first address for the first order and generates a corresponding second address for the second order based on sequences stored in the tables.

8199034, Jun 12, 2012

Apr 20, 2010

12/763709

Atul A. Salvekar - Emeryville CA, US
Young Geun Cho - Palo Alto CA, US
Jia Tang - Campbell CA, US
Shantanu Khare - Chicago IL, US
Ming-Chieh Kuo - San Diego CA, US
Iwen Yao - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H03M 7/00

341 50, 341 51

A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed.

8331892, Dec 11, 2012

Mar 5, 2009

12/398285

Tamer A. Kadous - San Diego CA, US
Iwen Yao - San Diego CA, US
Jibing Wang - San Diego CA, US
Weihong Jing - San Diego CA, US
Yong Li - San Diego CA, US

Qualcomm Incorporated - San Diego CA

H04B 1/10

4552341, 455296

A technique for performing AGC and DC compensation in a receiver. The receiver comprises an energy estimator for generating an estimate of the level of a received signal; an RF device to apply gain to the received signal; an AGC for controlling the RF device gain based on the energy estimation; a first DC compensation loop for finely adjusting the DC component of the received signal in fast or slow tracking mode (FTM or STM); and a second DC compensation loop for coarsely adjusting the DC component of the received signal. Three modes of AGC operations: In Acquisition, iterations of FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during signal timing detection. In Connected, long energy estimation, RF device gain adjustment, and STM fine and coarse DC adjustments are performed during superframe preamble. In Sleep, FTM fine DC adjustment, short energy estimation, and RF device gain adjustment are performed during superframe preamble.

8458380, Jun 4, 2013

Mar 2, 2009

12/396217

Arunava Chaudhuri - San Diego CA, US
Iwen Yao - San Diego CA, US
Jeremy H. Lin - San Diego CA, US
Remi Gurski - San Diego CA, US
Kevin W. Yen - San Diego CA, US

Qualcomm Incorporated - San Diego CA

G06F 3/00
G06F 9/46

710 52, 718102

A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

8520571, Aug 27, 2013

Mar 2, 2009

12/396270

Arunava Chaudhuri - San Diego CA, US
Iwen Yao - San Diego CA, US
Jeremy H. Lin - San Diego CA, US
Ali RostamPisheh - San Diego CA, US
Raghu Challa - San Diego CA, US
Hemanth Sampath - San Diego CA, US
Megan Wu - San Diego CA, US
Joseph Zanotelli - San Diego CA, US
Mrinal Nath - San Diego CA, US

Qualcomm Incorporated - San Diego CA

H04B 7/00

370310

A flexible and reconfigurable digital system (for example, a wireless modem) includes a set of sub-circuits. Each sub-circuit includes a task manager and an amount of configurable hardware circuitry for performing a type of operation on a data stream. The task manager of a sub-circuit can configure and control the configurable hardware of the sub-circuit. A central processor configures and orchestrates operation of the sub-circuits by maintaining a set of task lists in a tightly coupled memory. Each task list includes task instructions for a corresponding sub-circuit. The task manager of a sub-circuit reads task instructions from its task list and controls its associated hardware circuitry as directed by the instructions. A timestamp task instruction and a push task instruction and the task list architecture allow modem sub-circuits to be easily reconfigured to operate in accordance with either a first air interface standard or a second air interface standard.

8572332, Oct 29, 2013

Mar 16, 2009

12/404613

Ali RostamPisheh - San Diego CA, US
Raghu N. Challa - San Diego CA, US
Iwen Yao - San Diego CA, US
Davie J. Santos - Encinitas CA, US
Mrinal M. Nath - San Diego CA, US

Qualcomm Incorporated - San Diego CA

G06F 12/00

711154, 375341

A de-interleaver generates a plurality of De-interleaved Reorder Physical (DRP) addresses to simultaneously write a corresponding plurality of LLR values into a multi-banked memory such that not more than one LLR value is written into each bank of the multi-banked memory at a time. A sequence of such parallel writes results in the LLR values of a transmission of a sub-packet being stored in the memory. Address translation performed during generation of the DRP addresses causes the LLR values to be stored within the banks such that a decoder can read LLR values out of the memory in a de-interleaved sequence. Each memory location of a bank is a word-location for storing multiple related LLR values, where one LLR value is stored along with its parity values. The ability to simultaneously write to multiple LLR values is used to clear locations in a fast and efficient manner.

20090245334, Oct 1, 2009

Oct 30, 2008

12/261937

Arunava Chaudhuri - San Diego CA, US
Iwen Yao - San Diego CA, US
Jeremy H. Lin - San Diego CA, US
Remi Gurski - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

H04B 1/38

375222

A modem (for example, a modem within a cellular telephone) includes a plurality of Wireless Communication System Modem Sub-Circuits (WCSMSCs). Each WCSMSC receives a control signal generated by a corresponding one of a plurality of programmable timers. Each timer receives the same sequence of count values from a wall clock counter. A processor that controls overall modem operation can program a timer to generate a control pulse at a particular count time of the wall clock counter. The processor can also program a timer to generate a periodic control signal. The control signals output from the timers orchestrate when the various WCSMSCs start operating in the processing of a frame. By virtue of the programmability of the timers, the wall clock timer system is programmable to generate customized control signals such that frames of new and different protocols having arbitrary frame structures can be processed by the same modem/timer system.

20090248774, Oct 1, 2009

Mar 26, 2009

12/411728

Arunava Chaudhuri - San Diego CA, US
Hemanth Sampath - San Diego CA, US
Iwen Yao - San Diego CA, US
Jeremy H. Lin - San Diego CA, US
Raghu N. Challa - San Diego CA, US
Min Wu - San Diego CA, US

QUALCOMM Incorporated - San Diego CA

G06F 17/14

708404

An improved processing engine for performing Fourier transforms includes an instruction processor configured to process sequential instruction software commands and a Fourier transform engine coupled to the instruction processor. The Fourier transform engine is configured to perform Fourier transforms on a serial stream of data. The Fourier transform engine is configured to receive configuration information and operational data from the instruction processor via a set of software tasks.