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Yannick P Feurprier

from Watervliet, NY
Age ~56

Yannick Feurprier Phones & Addresses

  • 2301 Brooke Cir, Watervliet, NY 12189 (518) 326-6503
  • 17 Northern Blvd, Watervliet, NY 12189
  • East Greenbush, NY
  • Albany, NY

Work

Position: Clerical/White Collar

Education

Degree: High school graduate or higher

Publications

Us Patents

Method For Selective Removal Of Damaged Multi-Stack Bilayer Films

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US Patent:
7723237, May 25, 2010
Filed:
Dec 15, 2006
Appl. No.:
11/611611
Inventors:
Sandra Hyland - Guilderland NY, US
Ian J. Brown - Austin TX, US
Yannick Feurprier - East Greenbush NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
H01L 21/461
H01L 21/302
US Classification:
438706, 257E21215, 257E21241
Abstract:
A method for removing a damaged low dielectric constant material following an etch process, an ashing process, or a wet cleaning process is described. A dry, non-plasma removal process is implemented to remove a thin layer of damaged material on a feature following formation of the feature. The dry, non-plasma removal process comprises a chemical treatment of the damaged material, followed by a thermal treatment of the chemically treated surface layer. The two steps, chemical and thermal treatment, can be repeated.

Method For Forming A Damascene Structure

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US Patent:
7935640, May 3, 2011
Filed:
Aug 10, 2007
Appl. No.:
11/836977
Inventors:
Yannick Feurprier - Watervliet NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
H01L 21/302
H01L 21/461
US Classification:
438738, 438597, 438622, 438637, 438706, 438707, 438710, 438733, 438734, 438737
Abstract:
A method of forming a damascene structure comprises preparing a film stack on the substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiO) layer formed on the SiCOH-containing layer, and a first mask layer formed on the silicon oxide layer. A trench pattern is created in the first mask layer. The trench pattern in the first mask layer is transferred to the silicon oxide layer, and then the first mask layer is removed. A second mask layer is formed on the silicon oxide layer. A via pattern is formed in the second mask layer. The via pattern is transferred to the SiCOH-containing layer using a first etching process, and then the second mask layer is removed. The trench pattern is transferred to the SiCOH-containing layer using a second etching process with plasma formed from a process composition comprising NF.

Method For Etching Low-K Material Using An Oxide Hard Mask

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US Patent:
7947609, May 24, 2011
Filed:
Aug 10, 2007
Appl. No.:
11/836957
Inventors:
Yannick Feurprier - Watervliet NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
H01L 21/302
H01L 21/461
US Classification:
438738, 438597, 438622, 438637, 438706, 438707, 438710, 438733, 438734, 438737
Abstract:
A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiO) layer formed on the SiCOH-containing layer, and a mask layer formed on the silicon oxide layer. A pattern is created in the mask layer. Thereafter, the pattern in the mask layer is transferred to the silicon oxide layer using an etching process, and then the mask layer is removed. The pattern in the silicon oxide layer is transferred to the SiCOH-containing layer using a dry plasma etching process formed from a process composition comprising NF.

Method For Metallizing A Pattern In A Dielectric Film

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US Patent:
8080473, Dec 20, 2011
Filed:
Aug 29, 2007
Appl. No.:
11/846662
Inventors:
Yannick Feurprier - Watervliet NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
H01L 21/4763
US Classification:
438638, 438618, 438634, 257E21579
Abstract:
A method of patterning a film stack is described. The method comprises preparing a film stack on a substrate, wherein the film stack comprises a SiCOH-containing layer formed on the substrate, a silicon oxide (SiO) layer formed on the SiCOH-containing layer, and a mask layer formed on the silicon oxide layer. A pattern is created in the mask layer. Thereafter, the pattern in the mask layer is transferred to the silicon oxide layer using a first etching process, and then the mask layer is removed. The pattern in the silicon oxide layer is transferred to the SiCOH-containing layer using a second etching process formed from a process composition comprising NF. Thereafter, the silicon oxide layer is removed using a third etching process.

Method To Remove Capping Layer Of Insulation Dielectric In Interconnect Structures

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US Patent:
8202803, Jun 19, 2012
Filed:
Dec 11, 2009
Appl. No.:
12/636430
Inventors:
Yannick Feurprier - Watervliet NY, US
Douglas M. Trickett - Altamont NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
H01L 21/311
US Classification:
438700, 257E21214, 257774
Abstract:
A method for patterning an insulation layer and selectively removing a capping layer overlying the insulation layer is described. The method utilizes a dry non-plasma removal process. The dry non-plasma removal process may include a self-limiting process.

Low Damage Method For Ashing A Substrate Using Co/Co-Based Process

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US Patent:
7637269, Dec 29, 2009
Filed:
Jul 29, 2009
Appl. No.:
12/511832
Inventors:
Kelvin Zin - Albany NY, US
Masaru Nishino - Tokyo, JP
Chong Hwan Chu - Guilderland NY, US
Yannick Feurprier - Watervliet NY, US
Assignee:
Tokyo Electron Limited - Tokyo
International Classification:
B08B 6/00
US Classification:
134 12, 134 1, 134 11, 134 13, 134 2, 134 31, 134 34, 134 35, 134 36, 134 42, 134902, 216 67, 438706, 438710, 438711, 438725
Abstract:
A method for removing a mask layer and reducing damage to a patterned dielectric layer is described. The method comprises disposing a substrate in a plasma processing system, wherein the substrate has a dielectric layer formed thereon and a mask layer overlying the dielectric layer. A pattern is formed in the mask layer and a feature formed in the dielectric layer corresponding to the pattern as a result of an etching process used to transfer the pattern in the mask layer to the dielectric layer. The feature includes a sidewall with a first roughness resulting from the etching process. A process gas comprising COand CO is introduced into the plasma processing system, and plasma is formed. The mask layer is removed, and a second roughness, less than the first roughness, is produced by selecting a flow rate of the CO relative to a flow rate of the CO.

Trench And Hole Patterning With Euv Resists Using Dual Frequency Capacitively Coupled Plasma (Ccp)

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US Patent:
20170263443, Sep 14, 2017
Filed:
Mar 14, 2017
Appl. No.:
15/458476
Inventors:
- Tokyo, JP
Andrew W. Metz - Watervliet NY, US
Yannick Feurprier - Albany NY, US
Katie Lutker-Lee - Niskayuna NY, US
International Classification:
H01L 21/027
G03F 7/20
H01L 21/311
Abstract:
A method for treating a substrate is disclosed. The method includes forming a film stack on the substrate, the film stack comprising an underlying layer, a coating layer disposed above the underlying layer, and a patterning layer disposed above the coating layer. In the method, portions of the patterning layer are removed to form sidewalls of the patterning layer and expose portions of the coating layer, a carbon-containing layer is deposited on the exposed portions of the coating layer and non-sidewall portions of the patterning layer, and the carbon-containing layer and a portion of the coating layer are removed to expose other portions of the coating layer and the patterning layer. The method further includes repeating the deposition and removal of the carbon-coating layer at least until portions of the underlying layer are exposed.

Trench And Hole Patterning With Euv Resists Using Dual Frequency Capacitively Coupled Plasma (Ccp)

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US Patent:
20160293405, Oct 6, 2016
Filed:
Apr 1, 2016
Appl. No.:
15/088701
Inventors:
- Tokyo, JP
Andrew W. Metz - Watervliet NY, US
Yannick Feurprier - Albany NY, US
Katie Lutker-Lee - Niskayuna NY, US
International Classification:
H01L 21/027
G03F 7/20
H01L 21/311
Abstract:
A method for etching an antireflective coating on a substrate is disclosed. The substrate comprises an organic layer, an antireflective coating layer disposed above the organic layer, and a photoresist layer disposed above the antireflective coating layer. The method includes patterning the photoresist layer to expose a non-masked portion of the antireflective coating layer and selectively depositing a carbon-containing layer on the non-masked portions of the antireflective coating layer and on non-sidewall portions of the patterned photoresist layer. The method further includes etching the film stack to remove the carbon-containing layer and to remove a partial thickness of the non-masked portions of the antireflective coating layer without reducing a thickness of the photoresist layer. The method further includes repeating the selective depositing and etching, at least until the complete thickness of the non-masked portions of the antireflective coating layer is removed, to expose the underlying organic layer.
Yannick P Feurprier from Watervliet, NY, age ~56 Get Report