Wenxiao Tan

7479910, Jan 20, 2009

Sep 26, 2007

11/861856

Michael W. Heinks - New Brighton MN, US
Joel A. Anderson - Brooklyn Park MN, US
Wenxiao Tan - Murphy TX, US

Medtronic, Inc. - Minneapolis MN

H03M 3/00

341143, 341118, 341122, 341155, 341172

In general, this disclosure describes techniques for capacitive digit-to-analog converter (CAPDAC) resetting in an implantable medical device (IMD) analog-to-digital converter (ADC). The CAPDAC of an IMD ADC may occasionally be reset to increase the accuracy of its output. The output of the CAPDAC may be disconnected from a negative feedback input of an integrator and connected to a pseudo load during the reset. Disconnecting the CAPDAC from the negative feedback input of the integrator reduces the affect of the reset on the integrator. During the reset of the CAPDAC, the negative feedback input of integrator is coupled to a sample and hold capacitor, which temporarily provides an input approximately equal to a previous, e. g. , immediate, value of the output of CAPDAC prior to the reset. Thus, the resetting of the CAPDAC is done in such a manner that the affect of the reset on integrator is substantially reduced or eliminated.

7495508, Feb 24, 2009

Mar 12, 2007

11/716835

Wenxiao Tan - Murphy TX, US

Texas Instruments Incorporated - Dallas TX

H03K 5/00

327554, 327556

Switched capacitor notch filter circuits are disclosed. An example switched capacitor notch filter circuit described herein includes a switched capacitor amplifier to receive an input signal and a first feedback signal, to amplify the input signal and the first feedback signal, and to output an output signal, a first integrator to receive the output signal and a second feedback signal, to integrate the output signal and the second feedback signal, and to output the first feedback signal, a second integrator to receive the first feedback signal, to integrate the first feedback signal, and to output the second feedback signal, a sample and hold to receive the output signal, to periodically store a value of the output signal, and to output the value of the output signal, and a first switch to couple the sample and hold to the output signal when the sample and hold is to store the value of the output signal and to isolate the sample and hold from the output signal when the sample and hold is to output the value of the output signal.

7928703, Apr 19, 2011

Apr 30, 2009

12/433273

Wenxiao Tan - Murphy TX, US
Juergen Luebbe - Plano TX, US

Texas Instruments Incorporated - Dallas TX

G05F 1/613

323224, 323283, 323284

One embodiment of the invention includes an on-chip current-sense system for measuring a magnitude of an output current through a power transistor. The system includes a first sense transistor that conducts a first reference current to or from a phase node and a second sense transistor configured to conduct a second reference current to or from a power rail. The first and second sense transistors can be substantially identical and can be proportionally matched to the power transistor. An OTA receives the first and second reference currents and a third reference current that flows to or from the phase node and generates a sense current that is proportional to the output current in response to the first, second, and third reference currents. A sense circuit compares the sense current with a predetermined magnitude and generates an over-current signal in response to the sense current being greater than the predetermined magnitude to indicate an over-current condition of the output current.

8217615, Jul 10, 2012

May 5, 2009

12/435823

Wenxiao Tan - Murphy TX, US
Gregory Swize - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

G05F 1/10

318650, 31840001, 31840026, 31840027, 318801

One embodiment of the invention includes a disk-drive spindle motor power regulator system. The system includes a switching system comprising at least one power transistor for each of a plurality of phases of a disk-drive spindle motor. The system also includes a switching controller configured to generate a plurality of switching signals configured to control the at least one power transistor for each of the plurality of phases of the disk-drive spindle motor. The system further includes a current monitor configured to measure a magnitude of an individual phase current through at least one of the plurality of phases of the disk-drive spindle motor.

20130200954, Aug 8, 2013

Feb 5, 2013

13/759848

Texas Instruments Incorporated - Dallas TX, US
Wenxiao Tan - Murphy TX, US
Gregory Swize - Dallas TX, US

Texas Instruments Incorporated - Dallas TX

H03G 3/00

330279

A high performance digitalized Programmable Gain Amplifier (PGA). In prior art circuit, a dual-ladder DAC is employed for gain control, the back gate leakage of NMOS resistors in the fine ladder conquers fine ladder nominal current and it produces non-monotonic gain scallop. Two new art design techniques: (1) adaptively control the fine ladder; and (2) use dummy PMOS brunch device leakage compensates for the NMOS resistor device leakage, are proposed so that the non-monotonic scallops are substantially eliminated and 13-bit resolution/accuracy PGA has been achieved.

7474247, Jan 6, 2009

Sep 26, 2007

11/861945

Michael W. Heinks - New Brighton MN, US
Joel A. Anderson - Brooklyn Park MN, US
Wenxiao Tan - Murphy TX, US

Medtronic, Inc. - Minneapolis MN

H03M 1/12

341155, 341143

In general, this disclosure is related to detecting overload within an analog-to-digital converter (ADC) of an implantable medical device (IMD). The IMD may include an overload detection module that determines whether the ADC is operating in an overload condition. When the overload detection module determines the ADC is operating in the overload condition for a particular period of time, the ADC may send an overload signal to a processor that processes the output of the ADC. The overload signal notifies the processor that the ADC is operating in or is close to operating in the overload condition. In response to the indication from the ADC, the processor of the IMD may disregard the output of the ADC. The processor may continue to disregard the output of the ADC until the overload signal is deactivated, thereby indicating that the ADC is no longer in an overloaded condition.

20210028775, Jan 28, 2021

Oct 15, 2020

17/071803

- Dallas TX, US
Wenxiao Tan - Plano TX, US
Arun Rao - San Jose CA, US

H03K 4/48

Aspects provide for a circuit including a voltage supply, a driver, and a feedback bias circuit. The driver includes a first p-type field effect transistor (FET) and a first n-type FET. The voltage supply has an input and an output. The driver has a first input coupled to the voltage supply output, a second input coupled to a first node, and an output coupled to a second node. The first p-type FET has a gate coupled to the output of the driver, a source coupled to the voltage supply output, and a drain coupled to the second node. The first n-type FET has a gate coupled to the output of the second driver, a drain coupled to the second node, and a source coupled to a ground node. The feedback bias circuit has an input coupled to the second node and an output coupled to the voltage supply input.

20200106396, Apr 2, 2020

Dec 3, 2019

16/701502

- Dallas TX, US
Wenxiao TAN - Plano TX, US
Mayank GARG - Murphy TX, US
Toru TANAKA - Plano TX, US

H03F 1/30
H03F 3/04

An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.