Resumes
Resumes
Wayne Wennekamp Phones & Addresses
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Woodland Park, CO
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San Jose, CA
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1688 De Rose Way APT 1, San Jose, CA 95126 (505) 896-6845
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Publications
Us Patents
Parallel Interface For Configuring Programmable Devices
View pageUS Patent:
7358762, Apr 15, 2008
Filed:
May 18, 2005
Appl. No.:
11/131764
Inventors:
Steven K. Knapp - Soquel CA, US
Wayne E. Wennekamp - Rio Rancho NM, US
Wayne E. Wennekamp - Rio Rancho NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 38, 326 41
Abstract:
An interface between a programmable device and an external device coupled to the programmable device is described. The interface includes configurable control pins for providing control signals to the external device. The programmable device may be a field programmable gate array and the external device may be a nonvolatile memory. In some cases, the interface may be used to provide a byte-wide, or other parallel, interface. After configuration, the pins of the interface may be reclaimed and used for other purposes, such as accessing one or more external memories or other devices connected to a bus.
Integrated Circuit With A Selectable Interconnect Circuit For Low Power Or High Performance Operation
View pageUS Patent:
7893712, Feb 22, 2011
Filed:
Sep 10, 2009
Appl. No.:
12/556959
Inventors:
Chin Hua Tan - Sembawang, SG
Shankar Lakka - San Jose CA, US
Ronald L. Cline - Tijeras NM, US
James B. Anderson - Lubbock TX, US
Wayne E. Wennekamp - Rio Rancho NM, US
Shankar Lakka - San Jose CA, US
Ronald L. Cline - Tijeras NM, US
James B. Anderson - Lubbock TX, US
Wayne E. Wennekamp - Rio Rancho NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 41, 326 47, 326113
Abstract:
An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.
Method And Apparatus For Configurable Address Translation
View pageUS Patent:
8063660, Nov 22, 2011
Filed:
Jan 28, 2010
Appl. No.:
12/695341
Inventors:
Thomas H. Strader - San Jose CA, US
Schuyler E. Shimanek - Albuquerque NM, US
Wayne E. Wennekamp - Rio Rancho NM, US
Adam Elkins - Rio Rancho NM, US
Schuyler E. Shimanek - Albuquerque NM, US
Wayne E. Wennekamp - Rio Rancho NM, US
Adam Elkins - Rio Rancho NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/177
US Classification:
326 40, 326 41, 326 47
Abstract:
A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.
Method And Apparatus For Transferring Data To Or From A Memory
View pageUS Patent:
8307182, Nov 6, 2012
Filed:
Jan 19, 2010
Appl. No.:
12/689604
Inventors:
Thomas H. Strader - San Jose CA, US
Adam Elkins - Rio Rancho NM, US
Wayne E. Wennekamp - Rio Rancho NM, US
Schuyler E. Shimanek - Albuquerque NM, US
Adam Elkins - Rio Rancho NM, US
Wayne E. Wennekamp - Rio Rancho NM, US
Schuyler E. Shimanek - Albuquerque NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 13/00
US Classification:
711167, 711154, 711170
Abstract:
An embodiment of a technique to transfer data includes: operating a memory interface using memory access cycles that each include T successive time slots each provided for transfer of B bits of data, where T and B are positive integers; selecting one of first or second predetermined integers as one of T or B; and transferring a quantity of data Q between the memory interface and another interface. The transferring includes: automatically determining a value of M memory access cycles as a function of the one of T or B; causing a data transfer sequence on the memory interface that includes M successive memory access cycles and thus MT time slots; automatically determining a subset of the MT time slots as a function of the one of T or B; and transferring the quantity of data Q through the memory interface during the subset of time slots.