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Wallace E Lin

from Delray Beach, FL
Age ~73
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Also known as:
Lin E Wallace
Related to:
Edward D Lin, 71Ruth LinSuzanna L Lin, 71Laura Lin, 35Alison S King, 66Bryan M Lin, 37Gerald R King, 74M A LinCharles M King, 66Alison S King, 76
Connected to:
Aaron E Lin, 63Ai Lin, 70Angela X Lin, 52Antoine W Lin, 46Bennie Lin, 52Bevin Lin, 45Bi Q Lin, 48Bill T Lin, 70Blaise C Lin, 69Botao Lin, 41

Wallace Lin Phones & Addresses

  • Delray Beach, FL
  • 926 Mesa Oak Ct, Sunnyvale, CA 94086
  • Fort Lauderdale, FL
  • Santa Clara, CA

Professional Records

Lawyers & Attorneys

Wallace Lin Photo 1

Wallace Lin - Lawyer

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Office:
Wallace E. Lin
Specialties:
General Practice
ISLN:
905434962
Admitted:
1983
University:
Cornell University, B.A., 1973; University of Connecticut, M.B.A., 1976
Law School:
University of Connecticut, J.D., 1982
Wallace Lin Photo 2

Wallace Lin, Sunnyvale CA - Lawyer

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Office:
Wallace E. Lin
926 Mesa Oak Ct., Sunnyvale, CA
ISLN:
905434962
Admitted:
1983
University:
Cornell University, B.A.
Law School:
University of Connecticut, J.D.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Wallace Lin
Principal
Resources Unihmited
Business Services at Non-Commercial Site
773 W Remington Dr, Sunnyvale, CA 94087

Publications

Us Patents

Arrangements To Reduce Charging Damage In Structures Of Integrated Circuits

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US Patent:
6414358, Jul 2, 2002
Filed:
Sep 28, 2001
Appl. No.:
09/964616
Inventors:
Wallace W. Lin - San Jose CA
George E. Sery - San Francisco CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2362
US Classification:
257356, 257360, 257487
Abstract:
Arrangements to reduce charging damage in structures of integrated circuits (ICs).

Arrangements To Reduce Charging Damage In Structures Of Integrated Circuits Using Polysilicon Or Metal Plate(S)

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US Patent:
6566716, May 20, 2003
Filed:
Sep 28, 2001
Appl. No.:
09/964704
Inventors:
Wallace W. Lin - San Jose CA
George E. Sery - San Francisco CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2976
US Classification:
257355, 257288, 257328, 257356, 257360, 257367
Abstract:
Arrangements to reduce charging damage in structures of integrated circuits (ICs).

Architecture Of Data Communications Switching System And Associated Method

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US Patent:
6574194, Jun 3, 2003
Filed:
Jan 28, 1999
Appl. No.:
09/238711
Inventors:
Peter C. P. Sun - San Jose CA
Wallace Lin - San Jose CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
G01R 3108
US Classification:
370235, 370389, 370392
Abstract:
A system for facilitating packet data flow among stations on a data network and the associated method are disclosed. The system comprises queue managers that further comprise a free queue manager, an enqueue controller, a multicast queue manager, and a port queue manager. The free queue manager provides a mechanism to monitor the number of free buffers remaining in an external memory. The enqueue controller arbitrates between requests for enqueuing from the ports. The multicast queue manager maintains a multicast queue linked list and manages multicast queue entries to the list. The port queue manager manages output queues of each of the output ports and ensures that a packet is correctly routed to the appropriate ports for subsequent delivery. With the queue manages working in synchronization, an inbound packet can be routed to ports designated by the packet for delivery within a minimum time.

Arrangements To Reduce Charging Damage In Structures Of Integrated Circuits

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US Patent:
6624480, Sep 23, 2003
Filed:
Sep 28, 2001
Appl. No.:
09/964618
Inventors:
Wallace W. Lin - San Jose CA
George E. Sery - San Francisco CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 218234
US Classification:
257355, 257367
Abstract:
Arrangements to reduce charging damage in structures of integrated circuits (ICs).

Circuit Architecture And Method For Displaying Port Status In Data Communications Switching System

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US Patent:
6741593, May 25, 2004
Filed:
Jan 28, 1999
Appl. No.:
09/239210
Inventors:
Peter C. P. Sun - San Jose CA
Wallace Lin - San Jose CA
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H04L 1228
US Classification:
370392, 34081545
Abstract:
A system for displaying statuses for multiple signal paths or ports on LEDs is disclosed. The system comprising a plurality of shift circuits receives a data signal comprising groups of status signals. The data signal is serially shifted from one shift circuit to another so as to parse the status signals to be displayed on appropriate LEDs designated for each of the signal paths or ports. As a result, multiple statuses can be effectively displayed in real time using a minimum number of LEDs.

Charging Sensor Method And Apparatus

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US Patent:
6960784, Nov 1, 2005
Filed:
Jun 18, 2003
Appl. No.:
10/465741
Inventors:
Wallace W. Lin - San Jose CA, US
George E. Sery - San Francisco CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L023/58
US Classification:
257 48, 257288, 257356, 257360
Abstract:
A charging sensor is provided to detect charging signal during the manufacturing process of integrated circuits and various semiconductor devices. In one embodiment, the charging sensor includes a charging-sensitive insulator layer and complementary elements designed to effectively provide an indicative potential drop across the charging sensitive insulator.

Method For Protecting Circuits From Damage Due To Currents And Voltages During Manufacture

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US Patent:
7974055, Jul 5, 2011
Filed:
Oct 31, 2008
Appl. No.:
12/290483
Inventors:
Wallace W. Lin - San Jose CA, US
International Classification:
H02H 9/00
H02H 3/22
US Classification:
361 56, 361111
Abstract:
A protection circuit network includes one or more protection devices, used to protect one or more devices in an integrated circuit (IC) design. The protection devices are globally coupled together, for connection to an internal or external power supply. During manufacture of the IC, the protection circuit network protects the at-risk devices. During operation of the IC, the protection circuit network is powered down, such that excessive current leakage is avoided.

Evaluation Method For Interconnects Interacted With Integrated-Circuit Manufacture

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US Patent:
8001492, Aug 16, 2011
Filed:
Jun 27, 2008
Appl. No.:
12/215552
Inventors:
Wallace W. Lin - San Jose CA, US
Assignee:
Linden Design Technologies, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 51, 716136
Abstract:
A design and evaluation method for interconnect wires of integrated circuits is provided to detect, analyze and predict response of interconnect layout to integrated-circuit manufacture processes.
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Wallace E Lin from Delray Beach, FL, age ~73 Get Report