Wai Ting Chan

6353346, Mar 5, 2002

Oct 6, 2000

09/684754

Wai Cheong Chan - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03B 100

327112, 327206, 327170

An adaptive output driver that uses a programmable Schmitt-trigger buffer to change the drivers operational response after it is manufactured. The adaptive output driver includes a primary driver that provides the primary current to drive an output signal into a load. A secondary driver for the adaptive output driver is enabled by the Schmitt-trigger buffer to provide an additional current to drive the load when the transitions between high and low states are slower than a predetermined slew rate. The programmable Schmitt-trigger buffer includes cells of pull-up and pull-down transistors that can be separately enabled. Each enabled cell causes an imbalance in the overall sizing ratio of activated pull-up and pull-down transistors; the amount of imbalance in the overall sizing ratio corresponds to the amount of hysteresis in the response of the Schmitt-trigger buffer. By programming the amount of hysteresis in the Schmitt-trigger buffer, the operation of the adaptive output driver can be modified to suit different loading conditions after manufacture. The programmable Schmitt-trigger buffer can be used in the input stage of an input/output driver employed with a microprocessor.

6472912, Oct 29, 2002

Jan 4, 2001

09/755216

Hon Kin Chiu - Hayward CA
Wai Cheong Chan - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03K 1722

327143, 327198

A circuit for power supply detection and power on reset. The circuit comprises two separate component groups for producing separate currents which vary in response to the level of a voltage source. For example, each may have a non-linear DC relationship between the power supply and a current of the respective component groups. Furthermore, the DC voltage to current relationship of two groups is different. The circuit has an output with two modes. The two component groups are operable to force the output into one mode when the voltage source is above a threshold and a second mode when the voltage source is below the threshold. Therefore, the circuit is operable to detect when the supply voltage has dropped below a threshold and to also serve as a power on reset. However, the circuit does not rely on the threshold voltage of a transistor to trigger the output.

6600358, Jul 29, 2003

Aug 2, 2002

10/210940

Wai Cheong Chan - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03K 190185

327333, 326 81

In a level shifter for shifting from one voltage to another one, a circuit to eliminate current drain when the low voltage supply is off, includes circuitry for eliminating floating nodes and for providing a distinct output voltage. The circuit includes circuitry for monitoring the low voltage supply and switch in the level shifter when the supply is on. When the supply is off, the input is isolated from the output and an output signal derived from the high voltage supply is provided to the output.

6710622, Mar 23, 2004

Apr 12, 2002

10/121179

Wai Cheong Chan - Sunnyvale CA

National Semiconductor Corp - Santa Clara CA

H03K 19173

326 38, 326 46, 326 93

In a one-shot, the pulse duration is adjustable through the use of a counter and one or more programmable delay lines in one or more of the feedback loops of the one-shot. The one-shot makes use of at least two flip-flops, and the output of the counter resets the flip-flops.

6710637, Mar 23, 2004

Apr 29, 2002

10/134832

Wai Cheong Chan - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03K 3037

327259, 327258, 327239

In a non-overlap clock generator circuit providing two-phase clock signals, the clock-to-Q delay of memory elements is used to define the non-overlap times. The non-overlap time can be programmed in increments of the clock-to-Q delay of a standard memory element.

6720808, Apr 13, 2004

Nov 12, 2002

10/293136

Wai Chan - Sunnyvale CA

National Semiconductor Corporation - Santa Clara CA

H03K 1722

327143, 327198

A CMOS power up circuit for producing a power up signal for an integrated circuit device includes a plurality of transistor chains coupled to first and second select lines. The first and second select lines are configured to enable a selected one of the transistor chains. A VCC input is coupled to the transistor chains. An output latch is included in the power up circuit for generating a power up signal. The output latch is coupled to the transistor chains and to the VCC input and is configured to keep the power up signal deasserted until a voltage from the selected one transistor chain rises past a switch on threshold as VCC rises. When VCC rises past the switch on threshold, the output latch asserts the power up signal and maintains the power up signal asserted even if the voltage level of the VCC input temporarily droops below the switch on threshold.

6874933, Apr 5, 2005

Oct 15, 2002

10/272354

Wai Cheong Chan - Sunnyvale CA, US

National Semiconductor Corporation - Santa Clara CA

G01K007/00

374171, 374 1, 377 25, 331 66

A circuit for measuring temperature with all digital components in an integrated circuit. During manufacture, the number of clock period cycles during a known period of time at a predetermined temperature is stored in non-volatile memory. Later, during use of the integrated circuit, a clock circuit is activated and each cycle of its period is counted during a known length of time. Using the previously saved number of clock circuit cycles at a predetermined temperature and a current count of clock cycles for another known length of time, the current period of the clock circuit can be calculated and used to determine the current temperature.

6946881, Sep 20, 2005

Jun 14, 2002

10/171571

Wai Cheong Chan - Sunnyvale CA, US

National Semiconductor Corporation - Santa Clara CA

G01R019/00

327 28

In a polarity detector circuit for detecting the polarity of monitor sync signals, a clock generator and counter circuit are provided to count clock cycles during the positive and negative portions of the signal. Comparators are used to compare the counter values to predetermined values to determine when one or both of the counters has reached a predefined value. With the proper choice of sampling clock, this digital implementation can be easily optimized for small size and simplicity.