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Vivek Tiwari

from Saratoga, CA
Age ~53
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Related to:
Vayu TiwariAnika Tiwari, 22Gargi Choudhary, 54
Connected to:
Abhisek Tiwari, 39Ajeet Tiwari, 40Angela B Tiwari, 42Aniket Tiwari, 37Ankush Tiwari, 37Anupriya Tiwari, 42Apoorva Tiwari, 34Arjun Tiwari, 56Arvindkumar R Tiwari, 65Chandrashekhar Tiwari, 39

Vivek Tiwari Phones & Addresses

  • Saratoga, CA
  • Wilmington, DE
  • 1248 Heatherstone Ave, Sunnyvale, CA 94087 (408) 732-7952
  • 373 River Oaks Cir, San Jose, CA 95134 (408) 435-9060
  • 373 River Oaks Cir #502, San Jose, CA 95134 (408) 307-5312
  • 405 Camille Cir, San Jose, CA 95134 (408) 435-9060
  • 405 Camille Cir #17, San Jose, CA 95134 (408) 435-9060
  • 418 Galleria Dr, San Jose, CA 95134 (408) 435-9060
  • 418 Galleria Dr #2, San Jose, CA 95134
  • 733 Bounty Dr, San Mateo, CA 94404 (650) 522-8975
  • 733 Bounty Dr #201X, San Mateo, CA 94404 (650) 522-8975
  • Foster City, CA
  • Santa Clara, CA
  • Princeton, NJ

Work

Position: Executive, Administrative, and Managerial

Education

Degree: Bachelor's degree or higher

Emails

v***[email protected]

Publications

Us Patents

Method And Apparatus For Reducing The Power Consumed By A Processor By Gating The Clock Signal To Pipeline Stages

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US Patent:
6609209, Aug 19, 2003
Filed:
Dec 29, 1999
Appl. No.:
09/474461
Inventors:
Vivek Tiwari - Santa Clara CA
Vinod Sharma - San Jose CA
Sivakumar Makineni - Sunnyvale CA
Suri B. Medapati - San Jose CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 132
US Classification:
713322
Abstract:
A processor includes a pipeline having first and second stages and a shift register having first and second latches. An interface circuit is used to provide a clock signal from a clock signal line to the first and second stages based, at least in part, on first and second bits to be stored in the first and second latches, respectively.

Mechanism To Control Di/Dt For A Microprocessor

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US Patent:
6636976, Oct 21, 2003
Filed:
Jun 30, 2000
Appl. No.:
09/608748
Inventors:
Edward T. Grochowski - San Jose CA
David Sager - Portland OR
Vivek Tiwari - Foster City CA
Ian Young - Portland OR
David J. Ayers - Fremont CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 132
US Classification:
713320
Abstract:
The present invention provides a mechanism for adjusting the activity of an integrated digital circuit such as a processor to reduce voltage changes attributable to current changes triggered by clock gating. The processor includes one or more functional units and a current control circuit that monitors activity states of the processors functional units to estimate the current consumed over n clock cycles. The current control circuit estimates the current change for a given clock cycle from the n activity states and compares the estimated current change with first and second thresholds. The processors activity is decreased if the estimated current change is greater than the first threshold, and the processor activity is decreased if the estimated current change is less than the second threshold.

Multiple Mode Power Throttle Mechanism

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US Patent:
6931559, Aug 16, 2005
Filed:
Dec 28, 2001
Appl. No.:
10/041013
Inventors:
James S. Burns - Los Altos CA, US
Stefan Rusu - Sunnyvale CA, US
David J. Ayers - Fremont CA, US
Edward T. Grochowski - San Jose CA, US
Marsha Eng - Sunnyvale CA, US
Vivek Tiwari - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F001/32
US Classification:
713340, 713320, 713321, 710 15, 710 18
Abstract:
A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline, and to determine a power state for the processor from the monitored activity. One of two or more power control mechanisms is engaged, responsive to the power state of the processor reaching a threshold.

Simulation Of Di/Dt-Induced Power Supply Voltage Variation

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US Patent:
7020590, Mar 28, 2006
Filed:
Dec 28, 2001
Appl. No.:
10/041062
Inventors:
Edward T. Grochowski - San Jose CA, US
David J. Ayers - Fremont CA, US
Vivek Tiwari - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 17/50
G06F 13/00
US Classification:
703 2, 703 22, 702 57, 713322, 713323
Abstract:
A mechanism is disclosed for determining a voltage at a device in a power delivery network. The mechanism includes determining an impulse response for the power delivery network, and tracking the current consumed by the device as it operates over a sequence of clock cycles. The activity profile is filtered using a representation of the impulse response to provide a profile of the voltages at the device.

Mechanism For Estimating And Controlling Di/Dt-Induced Power Supply Voltage Variations

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US Patent:
7035785, Apr 25, 2006
Filed:
Dec 28, 2001
Appl. No.:
10/040582
Inventors:
Edward T. Grochowski - San Jose CA, US
David Sager - Portland OR, US
Vivek Tiwari - San Jose CA, US
Ian Young - Portland OR, US
David J. Ayers - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
703 18, 323364, 716 1, 716 6, 713322
Abstract:
A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

Mechanism For Estimating And Controlling Di/Dt-Induced Power Supply Voltage Variations

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US Patent:
7236920, Jun 26, 2007
Filed:
Dec 23, 2005
Appl. No.:
11/317948
Inventors:
Edward T. Grochowski - San Jose CA, US
David Sager - Portland OR, US
Vivek Tiwari - San Jose CA, US
Ian Young - Portland OR, US
David J. Ayers - Fremont CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
703 18, 323364, 716 1, 713322
Abstract:
A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

Digital Throttle For Multiple Operating Points

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US Patent:
7281140, Oct 9, 2007
Filed:
Dec 28, 2001
Appl. No.:
10/041092
Inventors:
James S. Burns - Los Altos CA, US
Stefan Rusu - Sunnyvale CA, US
David J. Ayers - Fremont CA, US
Edward T. Grochowski - San Jose CA, US
Marsha Eng - Sunnyvale CA, US
Vivek Tiwari - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/04
US Classification:
713300, 713323
Abstract:
A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the scaled activity. If the power state reaches a first threshold, the operating point of the processor is adjusted and a new scaling factor is selected to determine the power state.

Method And Apparatus To Limit Current-Change Induced Voltage Changes In A Microcircuit

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US Patent:
7685451, Mar 23, 2010
Filed:
Dec 20, 2002
Appl. No.:
10/327441
Inventors:
James S. Burns - Cupertino CA, US
Kenneth D. Shoemaker - Los Altos Hills CA, US
Sudarshan Kumar - Fremont CA, US
Tom E. Wang - Milpitas CA, US
David J. Ayers - Fremont CA, US
Vivek Tiwari - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/26
US Classification:
713340, 713300, 327538
Abstract:
A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

Amazon

Stratégie Pour Réussir Votre Laboratoire De Ccie: Le Guide Non-Technique (French Edition)

Stratégie pour réussir votre Laboratoire de CCIE: Le guide non-technique (French Edition)

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Votre stratégie de succès CCIE lab est un unique guide qui a été écrit par deux CCIEs doubles, et porte sur les aspects non techniques de l'examen CCIE Lab. En outre, il répond aux questions suivantes: • Où et comment puis-je commencer à préparer mon laboratoire CCIE? • Combien de temps dois-je prép...
Author

Vivek Tiwari, Dean Bahizad

Binding

Paperback

Pages

216

Publisher

CreateSpace Independent Publishing Platform

ISBN #

1479376175

EAN Code

9781479376179

ISBN #

5

Your Ccna Exam Success Strategy: The Non-Technical Guidebook For Routing & Switching

Your CCNA Exam Success Strategy: The Non-Technical Guidebook for Routing & Switching

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Your CCNA Exam Success Strategy: The Non-Technical Guidebook for Routing & Switching (preview at www.2doubleCCIEs.com) is a unique guidebook which has been written by two double CCIEs, and deals with the non-technical aspects of CCNA exam. In addition it answers the following questions : • How do I...
Author

Mr. Vivek Tiwari, Mr. Dean Bahizad

Binding

Paperback

Pages

204

Publisher

CreateSpace Independent Publishing Platform

ISBN #

1481162659

EAN Code

9781481162654

ISBN #

4

Your Ccie Lab Success Strategy: The Non-Technical Guidebook

Your CCIE Lab Success Strategy: The Non-Technical Guidebook

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Your CCIE lab Success strategy (preview at www.2doubleccies.com) is a unique guidebook which has been written by two double CCIEs, and deals with the non-technical aspects of CCIE Lab exam. In addition it answers the following questions : • Where and how do I start preparing for my CCIE Lab? • How...
Author

Mr. Dean Bahizad, Mr. Vivek Tiwari

Binding

Paperback

Pages

196

Publisher

CreateSpace Independent Publishing Platform

ISBN #

1470103168

EAN Code

9781470103163

ISBN #

2

Sdn And Openflow For Beginners With Hands On Labs

SDN and OpenFlow for beginners with hands on labs

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A vendor neutral book that answers the following questions and much more: • What is SDN? • How does SDN work? • What is the difference between SDN and OpenFlow? • How will SDN affect Enterprise and Datacenter networks? • Can I set my own lab to learn SDN? • What kind of a computer will I be needing ...
Author

Vivek Tiwari

Binding

Kindle Edition

Pages

156

ISBN #

1

Der Fünfte Beatle: Die Brian Epstein Story

Der fünfte Beatle: Die Brian Epstein Story

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Author

Andrew C. Robinson, Kyle Baker Vivek J. Tiwari

Binding

Hardcover

Publisher

Panini Verlags GmbH

ISBN #

3862017869

EAN Code

9783862017867

ISBN #

9

Fatigue And Corrosion In Metals

Fatigue and Corrosion in Metals

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Author

Tiwari Vivek

Binding

Hardcover

Pages

215

Publisher

Scitus Academics LLC

ISBN #

1681172178

EAN Code

9781681172170

ISBN #

7

Work-Related Attitudes: A Quantitative Analysis

Work-Related Attitudes: A Quantitative Analysis

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This work is an investigation which is directed to examine empirically the impact of the three work related attitudes viz., job satisfaction, motivation and job involvement on the organizational commitment of industrial workers. Then the impact of the two work related attitudes viz., job satisfactio...
Author

Vivek Tiwari, Surendra K. Singh

Binding

Paperback

Pages

252

Publisher

LAP LAMBERT Academic Publishing

ISBN #

3659257176

EAN Code

9783659257179

ISBN #

6

Sink Or Swim (Your Ccna Success Strategy Learning By Immersing Book 1)

Sink or Swim (Your CCNA Success Strategy Learning by Immersing Book 1)

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This book is for those entering the Networking arena by doing CCNA. Using the "Learning by Immersing" technique we give the reader a feel for the work that is done by network engineers. Besides the feel you also learn networking technologies in ways that makes it hard to forget. Small unique details...
Author

Vivek Tiwari

Binding

Kindle Edition

Pages

28

ISBN #

3

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Vivek Tiwari from Saratoga, CA, age ~53 Get Report