Inventors:
Vishal Sarin - Cupertino CA, US
Hieu Van Tran - San Jose CA, US
Isao Nojima - Los Altos CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 15/00
US Classification:
365 49, 365202, 365227, 36518907
Abstract:
A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage.
