Resumes
Resumes
Viraphol Chaiyakul Phones & Addresses
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11999 Oakview Way, San Diego, CA 92128 (858) 486-9592
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Carlsbad, CA
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565 Springbrook N, Irvine, CA 92614
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Lake Forest, CA
Business Records
Name / Title
Company / Classification
Phones & Addresses
Principal, Owner
Y Explorations Inc
Internet · Custom Computer Programing
Internet · Custom Computer Programing
25691 Atlantic Ocean Dr, Lake Forest, CA 92630
(949) 457-0294, (949) 457-0437
(949) 457-0294, (949) 457-0437
Publications
Us Patents
Systems And Methods For Improving Digital System Simulation Speed By Clock Phase Gating
View pageUS Patent:
8140316, Mar 20, 2012
Filed:
Nov 5, 2008
Appl. No.:
12/265661
Inventors:
Tauseef Kazi - San Diego CA, US
Haobo Yu - Irvine CA, US
Lukai Cai - San Diego CA, US
Mahesh Sridharan - San Diego CA, US
Viraphol Chaiyakul - San Diego CA, US
Haobo Yu - Irvine CA, US
Lukai Cai - San Diego CA, US
Mahesh Sridharan - San Diego CA, US
Viraphol Chaiyakul - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
G06F 17/50
G06F 3/00
G06F 3/00
US Classification:
703 16, 703 19, 716106, 716107
Abstract:
An apparatus for simulating digital systems is described. The apparatus includes a processor and memory in electronic communication with the processor. Instructions that are executable by the processor are stored in the memory. A simulation tool is started. The simulation tool is capable of simulating a plurality of components. A clock phase is adjusted to be turned off for at least one of the components. A digital system is simulated that includes the at least one component. The simulation does not simulate the clock phase for the at least one component.
Concurrent Multiple-Dimension Word-Addressable Memory Architecture
View pageUS Patent:
20080316835, Dec 25, 2008
Filed:
Jun 25, 2007
Appl. No.:
11/767639
Inventors:
Chihtung Chen - San Diego CA, US
Inyup Kang - San Diego CA, US
Viraphol Chaiyakul - San Diego CA, US
Inyup Kang - San Diego CA, US
Viraphol Chaiyakul - San Diego CA, US
International Classification:
G11C 8/02
G11C 7/18
G11C 7/18
US Classification:
36518905, 36523002
Abstract:
An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.
Concurrent Multiple-Dimension Word-Addressable Memory Architecture
View pageUS Patent:
20120134229, May 31, 2012
Filed:
Feb 8, 2012
Appl. No.:
13/368752
Inventors:
Chihtung Chen - San Diego CA, US
Inyup Kang - San Diego CA, US
Viraphol Chaiyakul - San Diego CA, US
Inyup Kang - San Diego CA, US
Viraphol Chaiyakul - San Diego CA, US
International Classification:
G11C 8/06
US Classification:
36523002, 3652385
Abstract:
An N-dimension addressable memory is disclosed. The memory includes an N-dimension array of bit ceils and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.