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Vijay C Jaswa

from Brooklyn, NY
Age ~73
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Also known as:
Vijay Dr Jaswa, Vijay Chinubhai Jaswa, Vijay Te Jaswa, Bijay Jaswa
Related to:
Rajiv Jaswa, 43Sonali Jaswa, 37Sandhya Jaswa, 69
Connected to:
Anil Jaswal, 48Dharmvir S Jaswal, 46Gagandeep S Jaswal, 40Maninder K Jaswal, 42Neha Jaswal, 35Raj Jaswal, 66Rajwant K Jaswal, 69Shruti Jaswal, 38Sonia Jaswal, 60Sunita Jaswal, 41

Vijay Jaswa Phones & Addresses

  • Brooklyn, NY
  • 19251 Valle Vista Dr, Saratoga, CA 95070 (408) 395-6678
  • 1052 Harlan Ct, San Jose, CA 95129
  • New York, NY
  • Clifton Park, NY
  • Santa Clara, CA
  • PO Box 3429, Saratoga, CA 95070

Business Records

Name / Title
Company / Classification
Phones & Addresses
Vijay Jaswa
President
TULLY COMPUTER SYSTEMS, INC
1430 Tully Rd Sw 417, San Jose, CA 95122
1430 Tully Rd, San Jose, CA 95122
Vijay Jaswa
President
EXSYS STORAGE SYSTEMS, INC
1290 Tully Rd #703, San Jose, CA 95122

Publications

Us Patents

High Performance Server Farm With Tagging And Pipelining

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US Patent:
7062570, Jun 13, 2006
Filed:
Aug 3, 2001
Appl. No.:
09/921460
Inventors:
Jack Hong - Cupertino CA, US
Albert Bonyao Chu - Morgan Hill CA, US
Vijay Jaswa - Saratoga CA, US
Assignee:
Avaya Technology, Corp. - Basking Ridge NJ
International Classification:
G06F 15/173
H04L 12/28
H04L 12/56
H04L 12/50
H04Q 11/00
US Classification:
709238, 709225, 709226, 370386, 370388, 370396
Abstract:
The present invention is directed to a network switch that determines when specific content is hot and directs flow to one or more cache servers. The architecture can include a tag generator to generate unique tags corresponding to a server in a plurality of servers, a content pre-fetching algorithm to retrieve information before the information is requested by determining the hotness of the information, and a cache server in which stored information is configured based upon the relative degrees of hotness of the stored information.

Non-Intrusive Multiplexed Transaction Persistency In Secure Commerce Environments

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US Patent:
7177945, Feb 13, 2007
Filed:
Aug 3, 2001
Appl. No.:
09/921832
Inventors:
Jack Hong - Cupertino CA, US
Albert Bonyao Chu - Morgan Hill CA, US
Vijay Jaswa - Saratoga CA, US
Assignee:
Avaya Technology Corp. - Basking Ridge NJ
International Classification:
G06F 15/173
US Classification:
709238, 709226, 370389
Abstract:
The present invention is directed to a network switch that determines when specific content is hot and directs flow to one or more cache servers. The architecture of the present invention includes a decryption processor for authenticating clients and decrypting and encrypting transaction requests before the transaction requests are routed by the switch.

Intelligent Demand Driven Recognition Of Url Objects In Connection Oriented Transactions

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US Patent:
7228350, Jun 5, 2007
Filed:
Aug 3, 2001
Appl. No.:
09/921458
Inventors:
Jack Hong - Cupertino CA, US
Albert Bonyao Chu - Morgan Hill CA, US
Vijay Jaswa - Saratoga CA, US
Assignee:
Avaya Technology Corp. - Basking Ridge NJ
International Classification:
G06F 15/173
H04L 12/28
US Classification:
709226, 709238, 370389
Abstract:
The present invention is directed to a network switch that determines when specific content is hot and directs flow to one or more cache servers. The architecture of the present invention can include a cache and a digest generator to store predetermined objects in the cache based on the digest generated by the digest generator.

System And Method For Enabling Redundancy In Pci-Express Architecture

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US Patent:
7370224, May 6, 2008
Filed:
Feb 17, 2005
Appl. No.:
11/060199
Inventors:
Vijay Jaswa - Sunnyvale CA, US
Jeffrey Kidd - Los Altos CA, US
Robert Haragan - Los Altos CA, US
Robert Ferrer - Sunnyvale CA, US
Assignee:
Alcatel USA Sourcing, Inc - DE
International Classification:
G06F 11/00
US Classification:
714 4, 710316
Abstract:
A method and system is provided to enable redundancy in the communication between a plurality of peripheral devices and redundant hosts through redundant switches. The peripheral devices and the host are connected through a Peripheral Component Interconnect Express (PCI-Express) architecture in a data processing system. In an embodiment of the invention, the system includes a switch, a redundant switch, and switch-level exchanging means. The switch-level exchanging means enables the exchange of data packets between the peripheral devices and the host, through an available switch. The available switch is either the switch or the redundant switch. In another embodiment of the invention, the system also includes a redundant host and host-level exchanging means. The host-level exchanging means enables the exchange of data packets between an available host and the available switch. The available host is either the host or the redundant host.

Booting Intelligent Components From A Shared Resource

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US Patent:
7574589, Aug 11, 2009
Filed:
May 5, 2005
Appl. No.:
11/123864
Inventors:
Vijay Jaswa - Saratoga CA, US
Jeffrey Kidd - Los Altos CA, US
Assignee:
Alcatel-Lucent USA Inc. - Murray Hill NJ
International Classification:
G06F 9/24
G06F 15/177
G06F 1/24
US Classification:
713 1, 713 2, 713100
Abstract:
Booting intelligent components from a shared resource is disclosed. In various embodiments, booting a line card from a system storage device includes obtaining access to the system storage device, downloading operational code from the system storage device, and releasing access of the system storage device. The downloaded operational code is used by the line card to boot.

Fault-Tolerant Real Time Clock

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US Patent:
46444980, Feb 17, 1987
Filed:
Sep 26, 1985
Appl. No.:
6/780539
Inventors:
James F. Bedard - Schenectady NY
Vijay C. Jaswa - Clifton Park NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
G06F 104
US Classification:
364900
Abstract:
Three hardware real time clock subcircuits are connected in a triple modular redundancy configuration to assure continued operation if one subcircuit fails. A power supply or processor failure will not cause a clock supplying other processors to fail. Output of voted master clock pulses to the counter in every subcircuit is inhibited until all power supplies are turned on and stabilized, and the time base of the real time clock pulses is variable. The output pulses of all subcircuits are voted on and the voter output is the real time clock. The master clock can be the processor clock.

Adjustable Gain Controller For Valve Position Control Loop And Method For Reducing Jitter

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US Patent:
45569568, Dec 3, 1985
Filed:
Sep 16, 1983
Appl. No.:
6/533644
Inventors:
Royston J. Dickenson - Scotia NY
Vijay C. Jaswa - Clifton Park NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
G05B 1304
US Classification:
364162
Abstract:
An adjustable gain controller for a steam turbine valve position control loop includes an electronic operator, a proportional controller, a derivative controller and an integral controller. A steam flow condition error signal is amplified by the reciprocal of the valve's regulation value. The amplified error signal is supplied to the electronic operator and to the integral controller. The electronic operator includes means for initially selecting a value of A and n and generating a gain factor from a nonlinear gain characteristic function utilizing those values in combination with the valve's regulation value and the normalized error signal. The electronic operator multiplies the amplified error signal by the gain factor and applies the resultant signal to the proportional controller and the derivative controller. The output signals from the proportional, derivative and integral controllers are summed together and that sum is input into an electrohydraulic valve actuator system. The electrohydraulic valve actuator directly positions the steam valve.

Concurrent Processor For Control

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US Patent:
45946515, Jun 10, 1986
Filed:
Jan 18, 1984
Appl. No.:
6/571757
Inventors:
Vijay C. Jaswa - Clifton Park NY
Charles E. Thomas - Scotia NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
G06F 900
US Classification:
364131
Abstract:
This computer architecture is optimized for computing the state transitions of a controller, whereas conventional computers are optimized for data manipulation. The concurrent processor for control efficiently implements both the continuous and discrete control functions and has a processing element with two parts, the continuous and discrete processing elements. An arbitrary number of processing elements in a linear array have nearest-neighbor communications, and a general purpose microprocessor is provided to interact with them. Continuous states are computed concurrently and there is provision for interaction between continuous and discrete controls.
Control profile
Vijay C Jaswa from Brooklyn, NY, age ~73 Get Report