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Vandana Sojrani Phones & Addresses

  • Cupertino, CA

Publications

Us Patents

Method To Perform Thermal Simulation Of An Electronic Circuit On A Network

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US Patent:
6931369, Aug 16, 2005
Filed:
May 1, 2001
Appl. No.:
09/846681
Inventors:
Jeffrey Robert Perry - Cupertino CA, US
Martin Garrison - San Jose CA, US
Richard Levin - Sunnyvale CA, US
Phil Gibson - Sunnyvale CA, US
Vandana A. Sojrani - San Jose CA, US
Khang Nguyen - San Jose CA, US
Wanda Carol Garrett - Morgan Hill CA, US
John D. Perzow - Fort Collins CO, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F017/50
US Classification:
703 18, 703 13, 703 14, 703 6, 716 4, 716 5
Abstract:
A method and apparatus for thermally simulating a circuit over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. One or more web pages that identify the components are then delivered to the browser over the network. The component and topology information may be used to generate a schematic diagram that is delivered in a web page to the user over the network. The user may thermally simulate the designed circuit. Many characteristics of the board may be adjusted to provide an accurate thermal simulation.

Creating A Pc Board (Pcb) Layout For A Circuit In Which The Components Of The Circuit Are Placed In The Determined Pcb Landing Areas

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US Patent:
6678877, Jan 13, 2004
Filed:
Aug 15, 2001
Appl. No.:
09/930883
Inventors:
Jeffrey Robert Perry - Cupertino CA
Martin Garrison - San Jose CA
Richard Levin - Sunnyvale CA
Phil Gibson - Sunnyvale CA
Vandana A. Sojrani - San Jose CA
Khang Nguyen - San Jose CA
Wanda Carol Garrett - Morgan Hill CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06F 1750
US Classification:
716 15, 716 16, 716 8, 326101, 361720, 361764
Abstract:
A method and apparatus for PCB layout of a circuit simulated over a network is provided. Techniques are provided for designing a circuit that satisfies user-specified functional requirements received over a network. Based on the specified requirements, components and a topology for constructing the circuit are automatically determined. The components determined during this operation have operational values such that, when the components are arranged according to the topology to form the circuit, the circuit satisfies the user-specified functional requirements. The components are placed on a PC board having landing areas designed to accommodate all of the anticipated component sizes for the type of circuit being designed. The PC board may be cropped to the desired size. The PCB may be cropped automatically or manually by the user.
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