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Valentin N Kosenko

from Mountain View, CA
Age ~64
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Also known as:
Valentin A Kosenko, Valentin Konseko
Phone and address:
465 Sierra Vista Ave, Mountain View, CA 94043
(650) 967-2706
Related to:
Estaban FriedmanSergiy Kozenko, 62Tobias FriedbergerLarissa Konakova, 63Anastasia Kosenko, 37
Connected to:
Dale M Kosenko, 48David L Kosenko, 61Frederick R Kosenko, 52Ergin Koseoglu, 46Benjamin J Koser, 41Della Koser, 32Devin Koser, 44Gail J Koser, 72Mitchell J Koser, 55Thomas G Kosevich, 62

Valentin Kosenko Phones & Addresses

  • 465 Sierra Vista Ave, Mountain View, CA 94043 (650) 967-2706
  • 181 Del Medio Ave, Mountain View, CA 94040
  • 777 San Antonio Rd, Palo Alto, CA 94303 (650) 739-0121
  • 777 San Antonio Rd #114, Palo Alto, CA 94303 (650) 739-0121
  • 3475 Ross Rd, Palo Alto, CA 94303 (650) 739-0121
  • Dayhoit, KY
  • East Brunswick, NJ
  • Sunnyvale, CA
  • Santa Clara, CA

Work

Company: Rigetti computing Apr 2019 Position: Lead integration engineer

Education

School / High School: National Research University of Electronic Technology (Miet) 1976 to 1982

Skills

Semiconductors • Design of Experiments • Product Development • Semiconductor Industry • Ic • Nanotechnology • Thin Films • Electronics • Characterization • Cross Functional Team Leadership

Industries

Semiconductors

Resumes

Resumes

Valentin Kosenko Photo 1

Lead Integration Engineer

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Location:
Palo Alto, CA
Industry:
Semiconductors
Work:
Rigetti Computing
Lead Integration Engineer
Allvia 1999 - 2011
Diretcor Process Development
Allvia 1999 - 2011
Senior Process Engineer
Education:
National Research University of Electronic Technology (Miet) 1976 - 1982
National Research University of Electronic Technology (Miet)
Masters, Physics
Skills:
Semiconductors
Design of Experiments
Product Development
Semiconductor Industry
Ic
Nanotechnology
Thin Films
Electronics
Characterization
Cross Functional Team Leadership

Publications

Us Patents

Dielectric Trenches, Nickel/Tantalum Oxide Structures, And Chemical Mechanical Polishing Techniques

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US Patent:
7964508, Jun 21, 2011
Filed:
Aug 21, 2008
Appl. No.:
12/196065
Inventors:
Sergey Savastiouk - San Jose CA, US
Valentin Kosenko - Palo Alto CA, US
James J. Roman - Sunnyvale CA, US
Assignee:
Allvia, Inc. - Sunnyvale CA
International Classification:
H01L 21/302
US Classification:
438692, 438691, 438693, 216 90
Abstract:
A portion of a conductive layer () provides a capacitor electrode (). Dielectric trenches () are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric () can be formed by anodizing tantalum while a nickel layer () protects an underlying copper () from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer () is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.

Structures With Through Vias Passing Through A Substrate Comprising A Planar Insulating Layer Between Semiconductor Layers

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US Patent:
8431431, Apr 30, 2013
Filed:
Jul 12, 2011
Appl. No.:
13/181006
Inventors:
Valentin Kosenko - Mountain View CA, US
Sergey Savastiouk - Saratoga CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 21/00
US Classification:
438 98
Abstract:
A through via contains a conductor () passing through a substrate (). The substrate can be SOI or some other substrate containing two semiconductor layers () on opposite sides of an insulating layer (B). The through via includes two constituent vias () formed from respective different sides of the substrate by processes stopping on the insulating layer (B). Due to the insulating layer acting as a stop layer, high control over the constituent vias' depths is achieved. Each constituent via is shorter than the through via, so via formation is facilitated. The conductor is formed by separate depositions of conductive material into the constituent vias from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the through-via depth, so the deposition is facilitated. Other embodiments are also provided.

Dielectric Trenches, Nickel/Tantalum Oxide Structures, And Chemical Mechanical Polishing Techniques

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US Patent:
8633589, Jan 21, 2014
Filed:
Oct 2, 2007
Appl. No.:
11/866186
Inventors:
Sergey Savastiouk - San Jose CA, US
Valentin Kosenko - Palo Alto CA, US
James J. Roman - Sunnyvale CA, US
Assignee:
Invensas Corporation - San Jose CA
International Classification:
H01L 23/48
US Classification:
257758, 257760, 257762, 257766, 257E23145
Abstract:
A portion of a conductive layer () provides a capacitor electrode (). Dielectric trenches () are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric () can be formed by anodizing tantalum while a nickel layer () protects an underlying copper () from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer () is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.

Dielectric Trenches, Nickel/Tantalum Oxide Structures,And Chemical Mechanical Polishing Techniques

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US Patent:
20070257367, Nov 8, 2007
Filed:
May 5, 2006
Appl. No.:
11/418801
Inventors:
Sergey Savastiouk - San Jose CA, US
Valentin Kosenko - Palo Alto CA, US
James Roman - Sunnyvale CA, US
International Classification:
H01L 23/52
H01L 23/48
H01L 29/40
H01L 21/4763
US Classification:
257758000, 438622000, 438629000
Abstract:
A portion of a conductive layer () provides a capacitor electrode (). Dielectric trenches () are formed in the conductive layer to insulate the capacitor electrode from those portions of the conductive layer which are used for conductive paths passing through the electrode but insulated from the electrode. Capacitor dielectric () can be formed by anodizing tantalum while a nickel layer () protects an underlying copper () from the anodizing solution. This protection allows the tantalum layer to be made thin to obtain large capacitance. Chemical mechanical polishing of a layer () is made faster, and hence possibly less expensive, by first patterning the layer photolithographically to form, and/or increase in height, upward protrusions of this layer.

Integrated Circuits With Conductive Features In Through Holes Passing Through Other Conductive Features And Through A Semiconductor Substrate

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US Patent:
20080136038, Jun 12, 2008
Filed:
Dec 6, 2006
Appl. No.:
11/567494
Inventors:
Sergey Savastiouk - San Jose CA, US
Valentin Kosenko - Palo Alto CA, US
James J. Roman - Sunnyvale CA, US
International Classification:
H01L 23/535
H01L 21/768
US Classification:
257774, 438639, 257E21577, 257E23168
Abstract:
A backside contact pad is formed in an integrated circuit, possibly designed initially with just top side contact pads (C), by forming an opening () through a top side contact pad (C) and the semiconductor substrate (). Conductive material () is formed in the opening and in contact with the top side pad. The conductive material also provides a backside contact pad (). Other embodiments are also provided.

Integrated Circuits With Conductive Features In Through Holes Passing Through Other Conductive Features And Through A Semiconductor Substrate

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US Patent:
20080164574, Jul 10, 2008
Filed:
Mar 19, 2008
Appl. No.:
12/051269
Inventors:
Sergey Savastiouk - San Jose CA, US
Valentin Kosenko - Palo Alto CA, US
James J. Roman - Sunnyvale CA, US
International Classification:
H01L 23/48
US Classification:
257621, 257E23011
Abstract:
A backside contact pad is formed in an integrated circuit, possibly designed initially with just top side contact pads (C), by forming an opening () through a top side contact pad (C) and the semiconductor substrate (). Conductive material () is formed in the opening and in contact with the top side pad. The conductive material also provides a backside contact pad (). Other embodiments are also provided.

Agitation Of Electrolytic Solution In Electrodeposition

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US Patent:
20080271995, Nov 6, 2008
Filed:
May 3, 2007
Appl. No.:
11/744046
Inventors:
Sergey Savastiouk - San Jose CA, US
Valentin Kosenko - Palo Alto CA, US
Alexander J. Berger - Palo Alto CA, US
International Classification:
C25D 21/10
C25D 17/00
C25D 21/12
US Classification:
204273, 205148, 700296
Abstract:
In a reverse pulse plating of a substrate (), the electrolytic solution is agitated with a greater power on forward pulses () than on reverse pulses (). An ultrasound agitation source () can be positioned at the bottom of the substrate () if the anode () is at the top. The ultrasound source may contact the substrate's bottom. Other features are also provided.

Substrates With Through Vias With Conductive Features For Connection To Integrated Circuit Elements, And Methods For Forming Through Vias In Substrates

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US Patent:
20120228778, Sep 13, 2012
Filed:
Mar 7, 2011
Appl. No.:
13/042186
Inventors:
Valentin Kosenko - Palo Alto CA, US
Sergey Savastiouk - Saratoga CA, US
International Classification:
H01L 23/48
H01L 21/441
US Classification:
257774, 438668, 257E23011, 257E21477
Abstract:
A through via () contains a conductor () passing through a substrate () for connection to an integrated circuit element. The through via consists of two segments () formed from respective different sides () of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer () into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.
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Valentin N Kosenko from Mountain View, CA, age ~64 Get Report