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Tobing Soebroto

from Cupertino, CA
Age ~60
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Also known as:
Soebroto Tobing, Tobing S, Tobing O
Phone and address:
7920 Festival Ct, Cupertino, CA 95014
(650) 938-6370
Related to:
Jonathan KurniawanStephanie Kurniawan, 27Adi Budianto, 43Jenifer Budianto, 32Lily SoebrotoJuliani Budianto, 53Chandrawati Soebroto, 63Rusli R Kurniawan, 66
Connected to:
Justin T Soechting, 57Rina Soeda, 39Anthony A Soeder, 57Belinda A Soeder, 51Jeff D Soeder, 65Kim W Soeder, 68Robert W Soeder, 56Ryan L Soeder, 27Marylane Y Soeffing, 82Katherine Soegandhi, 41

Tobing Soebroto Phones & Addresses

  • 7920 Festival Ct, Cupertino, CA 95014 (650) 938-6370
  • Milpitas, CA
  • San Jose, CA
  • 110 Oak Haven Pl, Mountain View, CA 94041 (650) 938-6370
  • Palo Alto, CA
  • Redmond, WA
  • Santa Clara, CA
  • Belmont, CA
  • Daly City, CA
  • Bothell, WA

Publications

Us Patents

Method And System For Providing An Architecture For Selecting And Using Components For An Electronic Design

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US Patent:
8495531, Jul 23, 2013
Filed:
Sep 1, 2011
Appl. No.:
13/224107
Inventors:
Jeffrey K. Ng - Cupertino CA, US
Tobing Soebroto - Cupertino CA, US
Adam R. Traidman - Mountain View CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
G06F 9/455
US Classification:
716100, 716132, 705 51, 705500
Abstract:
An improved approach is described for allowing designers to identify and utilize suitable IP for an electronic design. An architecture is provided that includes an IP portal and/or chip estimator to identify suitable IP from a catalog of IP, which is integrated with a hosted design environment to use and test that IP for the user's specific electronic design. An authorization mechanism may be used to control access to the IP from the IP catalog. This approach greatly enhances the probability that IP suppliers will be successfully connected with the target consumers of those IP blocks.

System And Method For Power Gating Of An Integrated Circuit

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US Patent:
7568177, Jul 28, 2009
Filed:
Oct 30, 2006
Appl. No.:
11/589229
Inventors:
Tobing Soebroto - Cupertino CA, US
Ankur Gupta - Santa Clara CA, US
Hendy Kosasih - Diamond Bar CA, US
Richard Chou - Cupertino CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
G11C 5/14
H03K 17/16
H03K 19/094
US Classification:
716 9, 716 10, 716 13, 716 14, 326 33, 326 41, 326 47, 326101, 326 80, 365226
Abstract:
Apparatus and method aspects for power gating of an integrated circuit (IC) include providing at least one I/O power pad of an IC with a switch arrangement. The at least one I/O power pad is utilized to control a power signal transfer to at least a portion of the IC.
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Tobing Soebroto from Cupertino, CA, age ~60 Get Report