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Tom A Heynemann

from Fort Collins, CO
Age ~56
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Also known as:
Thomas A Heynemann
Phone and address:
7681 Carlson Ct, Fort Collins, CO 80524
Related to:
Salome Heynemann, 24Rita B Heynemann, 56
Connected to:
David D Heyneman, 68Jacey L Heyneman, 54Daniel Heynen, 41Dominik Heynen, 41Jennifer A Heynen, 50Robin L Heyner, 61Kristen A Heyniger, 64Rachel A Heynneman, 41Kayla M Heynoski, 34Desiree G Heyns, 68

Tom Heynemann Phones & Addresses

  • 7681 Carlson Ct, Fort Collins, CO 80524
  • 1930 Derby Ct, Fort Collins, CO 80526
  • 3404 E Harmony Rd, Fort Collins, CO 80528
  • 695 Creek Ct, Boulder Creek, CA 95006 (831) 338-0257
  • Ben Lomond, CA
  • Weldona, CO
  • Santa Cruz, CA
  • Cupertino, CA
  • Santa Clara, CA

Skills

Emc • Design • Computer Hardware • Software

Industries

Computer Hardware

Resumes

Resumes

Tom Heynemann Photo 1

Tom Heynemann

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Location:
Fort Collins, CO
Industry:
Computer Hardware
Skills:
Emc
Design
Computer Hardware
Software

Publications

Us Patents

Method And Apparatus To Allow Dynamic Variation Of Ordering Enforcement Between Transactions In A Strongly Ordered Computer Interconnect

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US Patent:
7308522, Dec 11, 2007
Filed:
Jun 9, 2004
Appl. No.:
10/864617
Inventors:
Tom A. Heynemann - Boulder Creek CA, US
Jeffrey A. Sprouse - Mountain View CA, US
Michael W. Knowles - Santa Clara CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 13/36
US Classification:
710310, 710311, 710306
Abstract:
A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

Delegated Write For Race Avoidance In A Processor

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US Patent:
7890706, Feb 15, 2011
Filed:
Nov 16, 2004
Appl. No.:
10/990151
Inventors:
David J. Garcia - Los Gatos CA, US
Michael Knowles - Santa Clara CA, US
Tom A. Heynemann - Boulder Creek CA, US
Jeffrey A. Sprouse - Mountain View CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 13/14
US Classification:
711150, 711141, 710244, 714 12, 714797
Abstract:
In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.

Method And Apparatus To Allow Dynamic Variation Of Ordering Enforcement Between Transactions In A Strongly Ordered Computer Interconnect

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US Patent:
20030131174, Jul 10, 2003
Filed:
Dec 24, 2001
Appl. No.:
10/035983
Inventors:
Tom Heynemann - Boulder Creek CA, US
Jeffrey Sprouse - Mountain View CA, US
Michael Knowles - Santa Clara CA, US
International Classification:
G06F013/14
US Classification:
710/310000
Abstract:
A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

Method And Apparatus For Ensuring Multi-Threaded Transaction Ordering In A Strongly Ordered Computer Interconnect

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US Patent:
20030131175, Jul 10, 2003
Filed:
Dec 24, 2001
Appl. No.:
10/035988
Inventors:
Tom Heynemann - Boulder Creek CA, US
Jeffrey Sprouse - Mountain View CA, US
Michael Knowles - Santa Clara CA, US
International Classification:
G06F013/36
US Classification:
710/310000
Abstract:
A method and apparatus of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions, on which the read transaction request depends, pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.

Remote Configuration Of Persistent Memory System Att Tables

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US Patent:
20070078940, Apr 5, 2007
Filed:
Oct 5, 2005
Appl. No.:
11/243848
Inventors:
Samuel Fineberg - Palo Alto CA, US
Pankaj Mehra - San Jose CA, US
Rahul Nim - Freemont CA, US
Tom Heynemann - Boulder Creek CA, US
International Classification:
G06F 15/167
US Classification:
709216000
Abstract:
Various embodiments of systems and methods for remotely configuring network memory are disclosed. One method embodiment, among others, comprises identifying a first device as having authority to control a memory device from a remote location, and writing start-up or reset parameters to memory of the memory device from the remote location, wherein the start-up or reset parameters are used to enable remote control of the memory device corresponding to remote direct memory access (RDMA) operations.

Method And Apparatus To Allow Dynamic Variation Of Ordering Enforcement Between Transactions In A Strongly Ordered Computer Interconnect

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US Patent:
20080065799, Mar 13, 2008
Filed:
Nov 9, 2007
Appl. No.:
11/938116
Inventors:
Tom Heynemann - Boulder Creek CA, US
Jeffrey Sprouse - Mountain View CA, US
Michael Knowles - Santa Clara CA, US
International Classification:
G06F 13/14
US Classification:
710110000
Abstract:
A method of enforcing the ordering of read and write transactions for an adapter unit connected to a strongly-ordered bus. The adapter unit has a set of read buffers and write buffers. Initiator write transactions and target read completion transactions are performed on the bus in the original order in which the transactions are received. An initiator read transaction request is enqueued in the read buffer but selectively awaits the performance of one or more pending initiator write transactions in the write buffer before the read transaction request is presented to the bus. In this way, initiator write transactions on which the read transaction request depends and pending in the write buffer are retired to the bus before the initiator read transaction request is performed, thus assuring that the initiator read transaction request is not performed ahead of the initiator write transaction on which the read transaction request depends.
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Tom A Heynemann from Fort Collins, CO, age ~56 Get Report