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Sumir M Varma

from Hillsboro, OR
Age ~50
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Also known as:
Sumir J Varma, Sumir Varou, Varma Sumir
Phone and address:
14510 Kenwood Ct, Beaverton, OR 97006
(503) 430-0224
Related to:
Donald Vakulich, 65Leonard MerrillDebra Vakulich, 70Thelma Merrill
Connected to:
Abhijeet Varma, 51Abhishek Varma, 41Anilkumar C Varma, 45Chhavi Varma, 52Deepak Varma, 59Dharmendra H Varma, 62Gopal Varma, 41Jagdish C Varma, 107Manish Varma, 54Naresh K Varma, 63

Sumir Varma Phones & Addresses

  • 14510 Kenwood Ct, Beaverton, OR 97006 (503) 430-0224
  • 1840 192Nd Ave, Beaverton, OR 97006 (503) 259-9545
  • 1249 NW 7Th Ave, Hillsboro, OR 97124
  • 3039 Ashford Cir, Hillsboro, OR 97124 (503) 645-7885 (503) 617-5130
  • Point Roberts, WA
  • Fort Collins, CO
  • Rochester, NY
  • Allen, TX
  • Memphis, TN
  • Alviso, CA
  • 14510 SW Kenwood Ct, Beaverton, OR 97006

Work

Company: Fluke corporation Mar 2020 Position: Senior engineering manager - fluke microelectronics

Education

Degree: Master of Science, Masters School / High School: Portland State University 2009 to 2015 Specialities: Electrical Engineering, Management

Skills

Semiconductors • Photolithography • Spc • Semiconductor Industry • Yield • Design of Experiments • Manufacturing • Lithography • Semiconductor Process • Process Simulation • Process Integration • Thin Films • Metrology • Process Control • Project Planning • Silicon • Microelectronics • Jmp • Project Management • Characterization • Data Analysis • Quality Management • Failure Mode and Effects Analysis • Compound Semiconductors • Lithography Process Development and Inte... • Process Engineering • Cost Saving Projects • Mems • Yield Enhancement Projects • Integrated Circuits • Photoresist Technology • Liftoff Processing Expertise • Engineering Management • Research and Development • Internal Audit • Cross Functional Team Leadership • Continuous Improvement • Sem Expertise • Phemt Devices • Hbt and Phemt Device Technology

Ranks

Certificate: 6 Sigma Green Belt

Industries

Semiconductors

Resumes

Resumes

Sumir Varma Photo 1

Senior Engineering Manager - Fluke Microelectronics

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Location:
408 Arrowhead Dr, Santa Clara, CA
Industry:
Semiconductors
Work:
Fluke Corporation
Senior Engineering Manager - Fluke Microelectronics
Intel Corporation
Ramp Lithography Engineer
Broadcom
Staff Lithography Development Engineer
Triquint Semiconductor Nov 2013 - Jun 2014
Staff Process Engineer
Triquint Semiconductor Aug 2012 - Nov 2013
Lithography Section Manager
Education:
Portland State University 2009 - 2015
Master of Science, Masters, Electrical Engineering, Management Portland State University 1992 - 2000
Master of Science, Masters The University of Texas at Dallas
Master of Business Administration, Masters, Finance Rochester Institute of Technology
Bachelors, Bachelor of Science, Engineering
Skills:
Semiconductors
Photolithography
Spc
Semiconductor Industry
Yield
Design of Experiments
Manufacturing
Lithography
Semiconductor Process
Process Simulation
Process Integration
Thin Films
Metrology
Process Control
Project Planning
Silicon
Microelectronics
Jmp
Project Management
Characterization
Data Analysis
Quality Management
Failure Mode and Effects Analysis
Compound Semiconductors
Lithography Process Development and Integration
Process Engineering
Cost Saving Projects
Mems
Yield Enhancement Projects
Integrated Circuits
Photoresist Technology
Liftoff Processing Expertise
Engineering Management
Research and Development
Internal Audit
Cross Functional Team Leadership
Continuous Improvement
Sem Expertise
Phemt Devices
Hbt and Phemt Device Technology
Certifications:
6 Sigma Green Belt
American Society of Quality

Publications

Us Patents

Hbt/Fet Process Integration

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US Patent:
7977708, Jul 12, 2011
Filed:
Nov 15, 2007
Appl. No.:
11/941065
Inventors:
Timothy Henderson - Portland OR, US
Jeremy Middleton - Beaverton OR, US
Sumir Varma - Beaverton OR, US
Corey Jordan - Portland OR, US
Gerard Mahoney - Beaverton OR, US
Bradley Avrit - Hillsboro OR, US
Lucius Rivers - Portland OR, US
Assignee:
Triquint Semiconductor, Inc. - Hillsboro OR
International Classification:
H01L 29/66
US Classification:
257195, 257192, 257197, 257E29171, 257E29218
Abstract:
A co-integrated HBT/FET apparatus and system, and methods for making the same, are disclosed. A co-integrated HBT/FET apparatus may include a first epitaxial structure formed over a substrate, the first epitaxial structure forming, at least in part, a FET device, a separation layer formed over the first epitaxial structure, and a second epitaxial structure formed over the separation layer, the second epitaxial structure forming, at least in part, a heterojunction bipolar transistor (HBT) device.
Control profile
Sumir M Varma from Hillsboro, OR, age ~50 Get Report