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Sujeet V Ayyapureddi

from Boise, ID
Age ~46
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Also known as:
Sujeet Y Ayyapureddi, T I, V I, Sujeet T
Phone and address:
6459 S Hornbeam Pl, Boise, ID 83716
(208) 343-6950
Connected to:
Easwar N Ayyar, 47Sheela D Ayyaru, 59Lenin Ayyasami, 51Manikandan Ayyasamy, 44Sunil L Ayyasamy, 55Mohammad Ayyash, 42Ganesh Ayyengar, 61Cengiz Ayyildiz, 36Najet T Ayyoub, 58Sanaa Ayyoub, 39

Sujeet Ayyapureddi Phones & Addresses

  • 6459 S Hornbeam Pl, Boise, ID 83716 (208) 343-6950
  • 4307 S Stargazer Pl, Boise, ID 83716
  • Wilbraham, MA
  • Toledo, OH

Education

Degree: Masters School / High School: The University of Toledo 2000 to 2002 Specialities: Electrical Engineering

Skills

Leadership • Research • Cmos Custom Circuit Design • Dram Design • Memory Array and Redundancy • Die Architecture • High Performance Memories • Power Delivery and Analysis • Full Chip Verification and Debug • High Speed I/O Transmitters • Hybrid Memory Cube • Microsoft Office • Vlsi • Integrated Circuit Design • Sense Amps • Cadence Virtuoso • Cmos • Pre and Post Silicon Validation

Industries

Semiconductors

Resumes

Resumes

Sujeet Ayyapureddi Photo 1

Sujeet Ayyapureddi

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Location:
Boise, ID
Industry:
Semiconductors
Education:
The University of Toledo 2000 - 2002
Masters, Electrical Engineering A.u.m.s.n.p.g.centre, Kkd 1996 - 2000
Bachelors
Skills:
Leadership
Research
Cmos Custom Circuit Design
Dram Design
Memory Array and Redundancy
Die Architecture
High Performance Memories
Power Delivery and Analysis
Full Chip Verification and Debug
High Speed I/O Transmitters
Hybrid Memory Cube
Microsoft Office
Vlsi
Integrated Circuit Design
Sense Amps
Cadence Virtuoso
Cmos
Pre and Post Silicon Validation

Publications

Us Patents

Reduction Of Fusible Links And Associated Circuitry On Memory Dies

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US Patent:
7102955, Sep 5, 2006
Filed:
Jan 30, 2006
Appl. No.:
11/343525
Inventors:
Sujeet V Ayyapureddi - Boise ID, US
Vasu Seeram - Colorado Springs CO, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 8/00
G11C 7/00
G11C 17/18
G11C 7/10
G06F 12/02
G06F 11/00
US Classification:
36523001, 365200, 3652257, 36523003, 3652385, 711200, 711202, 714 17, 714 38
Abstract:
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Reduction Of Fusible Links And Associated Circuitry On Memory Dies

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US Patent:
7102956, Sep 5, 2006
Filed:
Jan 30, 2006
Appl. No.:
11/343526
Inventors:
Sujeet V Ayyapureddi - Boise ID, US
Vasu Seeram - Colorado Springs CO, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 8/00
G11C 7/00
G11C 17/18
G11C 7/10
G06F 12/02
G06F 11/00
US Classification:
36523001, 365200, 3652257, 36523003, 3652385, 711200, 711202, 714 17, 714 38
Abstract:
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Reduction Of Fusible Links And Associated Circuitry On Memory Dies

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US Patent:
7102957, Sep 5, 2006
Filed:
Jan 30, 2006
Appl. No.:
11/343527
Inventors:
Sujeet V Ayyapureddi - Boise ID, US
Vasu Seeram - Colorado Springs CO, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 8/00
G06F 12/02
G06F 11/00
G11C 11/06
G11C 7/00
G11C 7/10
G11C 17/18
US Classification:
36523001, 365200, 3652257, 36523003, 3652385, 711200, 711202, 714 17, 714 38
Abstract:
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Reduction Of Fusible Links And Associated Circuitry On Memory Dies

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US Patent:
7388801, Jun 17, 2008
Filed:
Jan 30, 2006
Appl. No.:
11/343517
Inventors:
Sujeet V Ayyapureddi - Boise ID, US
Vasu Seeram - Colorado Springs CO, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 8/00
G11C 7/00
G06F 11/00
G11C 7/18
US Classification:
36523001, 365200, 3652257, 36523003, 714 6
Abstract:
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Dynamically Adjusting Operation Of A Circuit Within A Semiconductor Device

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US Patent:
7573288, Aug 11, 2009
Filed:
Sep 17, 2007
Appl. No.:
11/856352
Inventors:
Sujeet Ayyapureddi - Boise ID, US
Raghukiran Sreeramaneni - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03K 17/16
US Classification:
326 30, 326 87
Abstract:
Systems and methods for dynamically adjusting operation of a circuit within a semiconductor device are described herein. At least some illustrative embodiments include a system that includes a matching circuit including a first plurality of switching devices coupled to each other in parallel and not coupled in parallel to a resistive device, a driver circuit including a plurality of driver devices (the driver circuit adjusted based upon which of the switching devices are enabled), and processing logic that couples to the matching and driver circuits. The processing logic derives a binary value indicative of which of the switching devices are to be enabled, the binary value reflecting one or more process corners associated with the switching devices, and not reflecting one or more process corners associated with the resistive device. The processing logic further maps the binary value to a control value used to adjust the driver circuit.

Dynamically Adjusting Operation Of A Circuit Within A Semiconductor Device

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US Patent:
7804324, Sep 28, 2010
Filed:
Aug 11, 2009
Appl. No.:
12/539317
Inventors:
Sujeet Ayyapureddi - Boise ID, US
Raghukiran Sreeramaneni - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H03K 17/16
US Classification:
326 30, 326 87
Abstract:
Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device coupled to each other in parallel; a second plurality of switching devices coupled to each other in parallel and coupled in series with the reference circuit between a supply node and a supply return node; and processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance of the reference circuit than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices.

System And Method For Automatically Calibrating A Temperature Sensor

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US Patent:
7809519, Oct 5, 2010
Filed:
Jul 18, 2005
Appl. No.:
11/183684
Inventors:
Manoj Sinha - Boise ID, US
Sujeet Ayyapureddi - Boise ID, US
Brandon Roth - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G01K 15/00
US Classification:
702 99
Abstract:
There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system made up of a temperature sensor which includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.

Sharing Physical Memory Locations In Memory Devices

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US Patent:
7864577, Jan 4, 2011
Filed:
Mar 16, 2007
Appl. No.:
11/724855
Inventors:
Sujeet Ayyapureddi - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G11C 16/06
G06F 13/00
US Classification:
36518509, 365 96, 3652257, 711104, 711105
Abstract:
A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.
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Sujeet V Ayyapureddi from Boise, ID, age ~46 Get Report