Sudarshan T Kumar

6351151, Feb 26, 2002

Jul 18, 2001

09/909104

Sudarshan Kumar - Fremont CA
Wenjie Jiang - Sunnyvale CA

Intel Corporation - Santa Clara CA

H03K 19096

326 98, 326 95

A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

6369616, Apr 9, 2002

Jun 21, 2000

09/599050

Jiann-Cherng James Lan - San Jose CA
Sudarshan Kumar - Fremont CA

Intel Corporation - Santa Clara CA

H03K 19096

326 98, 326121, 326 83

A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. The shared pull-up transistor may be used to precharge an output node of the circuit. This circuit may be found useful in clock buffering applications.

6593776, Jul 15, 2003

Aug 3, 2001

09/922434

Sudarshan Kumar - Fremont CA
Gaurav Mehta - Folsom CA
Vivek Joshi - Sunnyvale CA

Intel Corporation - Santa Clara CA

H03K 1994

326105, 326106, 326107, 326108

A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

6628539, Sep 30, 2003

May 31, 2001

09/872975

Sudarshan Kumar - Fremont CA
Gaurav G. Mehta - Folsom CA
Sadhana Madhyastha - Los Altos CA
Jiann-Cherng Lan - San Jose CA

Intel Corporation - Santa Clara CA

G11C 1900

365 78, 365154, 36518912, 365240, 711127

A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

6629194, Sep 30, 2003

May 31, 2001

09/872965

Sudarshan Kumar - Fremont CA
Gaurav G. Mehta - Folsom CA
Sadhana Madhyastha - Los Altos CA
Jiann-Cherng Lan - San Jose CA

Intel Corporation - Santa Clara CA

G06F 1200

711104, 711 5, 36518525, 36523003, 36523066

A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.

6631093, Oct 7, 2003

Jun 29, 2001

09/895361

Sudarshan Kumar - Fremont CA
Jiann-Cherng Lan - San Jose CA
Wenjie Jiang - San Jose CA
Gaurav Mehta - Folsom CA
Sadhana Madhyastha - Santa Clara CA

Intel Corporation - Santa Clara CA

G11C 700

365203, 365204

A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.

6707318, Mar 16, 2004

Mar 26, 2002

10/107740

Sudarshan Kumar - Fremont CA
Shahram Jamshidi - Cupertino CA

Intel Corporation - Santa Clara CA

H03K 19096

326 98, 326 95

An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.

6820106, Nov 16, 2004

Jun 27, 2000

09/604620

Narsing K. Vijayrao - Santa Clara CA
Chi Keung Lee - San Jose CA
Sudarshan Kumar - Fremont CA

Intel Corporation - Santa Clara CA

G06F 738

708497, 708501

A method and apparatus to increase the performance of a floating point multiplier accumulator (FMAC). The method comprises receiving three floating point numbers and computing a product of the first floating point number and the second floating point number and adding a third floating point number to produce a sum value and a carry value. A propagate value, a kill value and a generate value are then computed based on the sum value and the carry value. Simultaneously the sum value is added to the carry value to create a first result, the sum value is added to the carry value and incremented by one to create a second result, the sum value is added to the carry value and incremented by two to create a third result, and a decimal point position is determined. One of the first result, the second result and the third result is then selected responsive to a rounding mode and the decimal point position. The selected result is normalized based on the decimal point position.