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Stephen T Janesch

from Greensboro, NC
Age ~62
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Also known as:
Stephen Thomas Janesch, Stephen J Janesch, Steve T Janesch, Stephen H
Phone and address:
7702 Wilder Ct, Greensboro, NC 27409
(336) 662-0104
Related to:
Marie R Janesch, 93Alan Janesch, 70Donna Janesch, 69Ann L Lohr, 65Ann Janesch, 65Frank Janesch
Connected to:
Maria T Janesch, 80Aleksandra JaneskaRonald J Janeski, 56Erik C Janesky, 39Wendy S Janesky, 57David M Janet, 58Ernie J Janet, 75Jacob D Janet, 29Jacqueline M Janet, 62Laura M Janet, 40

Stephen Janesch Phones & Addresses

  • 7702 Wilder Ct, Greensboro, NC 27409 (336) 662-0104
  • 1921 New Garden Rd, Greensboro, NC 27410
  • Austin, TX
  • 5177 Tilghman St, Coopersburg, PA 18036
  • Syracuse, NY
  • 7702 Wilder Ct, Greensboro, NC 27409

Work

Company: Triad semiconductor Mar 2012 Position: Principal design engineer

Education

Degree: Masters, Master of Science In Electrical Engineering School / High School: Syracuse University 1985 to 1988 Specialities: Engineering

Skills

Analog • Circuit Design • Ic • Cmos • Rf • Electronics • Semiconductors • Layout • Simulations • Bicmos • Mixed Signal • Analog Circuit Design • Asic • Lna • Testing • Microwave • Microelectronics • Amplifiers • Rf Engineering • Embedded Systems • Soc • Characterization • Integrated Circuit Design

Industries

Semiconductors

Resumes

Resumes

Stephen Janesch Photo 1

Greensboro And Winston-Salem, North Carolina

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Location:
Greensboro, NC
Industry:
Semiconductors
Work:
Triad Semiconductor
Principal Design Engineer
Rfmd Aug 1999 - Feb 2012
Principal Engineer
Nokia 1998 - 1999
Member of Technical Staff
Amd 1995 - 1998
Member of Technical Staff
Lockheed Martin 1993 - 1995
Senior Microwave Engineer
Education:
Syracuse University 1985 - 1988
Masters, Master of Science In Electrical Engineering, Engineering Penn State University 1981 - 1985
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering The Cooper Union For the Advancement of Science and Art 1980 - 1981
Skills:
Analog
Circuit Design
Ic
Cmos
Rf
Electronics
Semiconductors
Layout
Simulations
Bicmos
Mixed Signal
Analog Circuit Design
Asic
Lna
Testing
Microwave
Microelectronics
Amplifiers
Rf Engineering
Embedded Systems
Soc
Characterization
Integrated Circuit Design

Publications

Us Patents

Apparatus And Method To Reduce Power Amplifier Noise Generation In A Multiplexed Communication System

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US Patent:
6404824, Jun 11, 2002
Filed:
Dec 16, 1998
Appl. No.:
09/212744
Inventors:
Eddy Kent Bell - Round Rock TX
Stephen T. Janesch - Coopersburg PA
Assignee:
Legerity, Inc. - Austin TX
International Classification:
H04B 144
US Classification:
375297, 370278, 370282, 455 83, 455127
Abstract:
In order to reduce the noise components in a multiplexed communication system, noise components generally referred to as splatter that from the rapid transition between the transmitting state and the non-transmitting state, this power transition in the transmitted signal is provided with a ramped envelope. In the preferred embodiment, the ramped power transition is the result of a ramped enabling signal applied to the power amplifier generating the transmitted signal. The use of a ramped power transition reduces the noise introduced as a result of an abrupt power transition. In addition, the transmitted signal is provided with a preamble so that no data is transmitted during the transition period.

Alias Suppression Method For 1-Bit Precision Direct Digital Synthesizer

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US Patent:
6518801, Feb 11, 2003
Filed:
Aug 5, 1999
Appl. No.:
09/368172
Inventors:
Stephen T. Janesch - Coopersburg PA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03B 2100
US Classification:
327105, 327317, 327551
Abstract:
The present invention provides an improved apparatus and technique for removing alias signals from the output of a discretely timed circuit. Rather than simply lowpass filtering an output signal from a discretely timed circuit signal to remove aliases as in conventional discretely timed circuits, and instead of increasing the frequency of the clock signal in other conventional discretely timed circuits, the present invention provides for interpolation between clock edges, taking advantage of information in the digital representation, to reduce or eliminate many lower-order alias signal components. More particularly, the present invention eliminates lower-order aliases of a discretely timed circuit, e. g. , of a 1-bit resolution direct digital synthesizer (DDS) by interpolating transitions within clock periods utilizing the period of the signal and its instantaneous phase, to improve the time resolution of the output signal. In a disclosed embodiment, a multiplier produces product of an output signal (e. g.

Apparatus And Method For Broadcast Band Noise Reduction In A Transmitter With A Low If Frequency

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US Patent:
6532270, Mar 11, 2003
Filed:
Dec 16, 1998
Appl. No.:
09/212903
Inventors:
Eddy Kent Bell - Round Rock TX
Stephen T. Janesch - Coopersburg PA
Assignee:
Legerity, Inc. - Austin TX
International Classification:
H03C 152
US Classification:
375301, 332170, 455109
Abstract:
In the broadcast band having a plurality of channels allocated therein, by using high-side injection and low-side injection as described herein, the noise introduced into the channel by the local oscillator signal can be minimized. The local oscillator signal in combination with the intermediate frequency determines the frequency of the channel signal being produced by the transmitter. The selected high-or low-side injection determines whether the bulk of the power is introduced into the combination frequency signal (i. e. , the channel) above or below the local oscillator frequency, thereby moving the local oscillator frequency outside the broadcast band. The non-selected sideband is even further outside broadcast band.

Compensation Of Frequency Pulling In A Time-Division Duplexing Transceiver

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US Patent:
6597754, Jul 22, 2003
Filed:
Dec 21, 1998
Appl. No.:
09/217233
Inventors:
Stephen T. Janesch - Coopersburg PA
Paul Schnizlein - Austin TX
Assignee:
DSP Group, Inc. - Santa Clara CA
International Classification:
H03D 324
US Classification:
375376, 375326, 375327
Abstract:
A carrier-recovery loop for compensating frequency pulling in TDD and TDMA radio transceivers. The digital carrier-recovery loop includes a signal input, a digitally-controlled oscillator (DCO), a phase detector, a loop filter, and a memory. The memory stores an initializing value for the DCO, so that its frequency can be rapidly initialized at the start of a received frame. This initializing value is preferably either a sample of a control signal for the DCO, or a sample of the integrated value of a phase-error signal generated by the phase detector. Also described is a method for compensating the frequency pulling in a TDD or TDMA radio transceiver. The transceiver preferably receives data frames that have a preamble followed by a payload portion that holds the transmitted data. The method includes steps of (a) performing a carrier recovery during the preamble of a received frame, (b) storing a digital word indicative of a recovered carrier frequency at the end of the preamble, (c) continuing the carrier recovery during the payload portion of the received frame, (d) using the stored digital word to set an initial frequency for carrier recovery at the start of a subsequent frame, and (e) repeating said steps (a)-(d) for each frame in the series of data frames.

Phase Locked Loop With Numerically Controlled Oscillator Divider In Feedback Loop

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US Patent:
6650721, Nov 18, 2003
Filed:
Aug 5, 1999
Appl. No.:
09/368583
Inventors:
Stephen T. Janesch - Coopersburg PA
Carl R. Stevenson - Macungie PA
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03D 324
US Classification:
375376, 375375, 327156
Abstract:
A digital phase locked loop (PLL) frequency synthesizer includes a 1-bit numerically controlled oscillator (NCO) to negate the requirement that a VCO frequency be an integer multiple of its reference frequency. Thus, in accordance with the principles of the present invention, a direct digital synthesizer (DDS) or numerically controlled oscillator (NCO) is used to form a frequency divider in a feedback path of a PLL. Thus, a synthesizer with fine frequency control and very fast settling time is disclosed. The conventional integer-ratio relationship between the reference frequency f and the synthesized output frequency signal f is overcome by replacement of a conventional VCO divider in a feedback path of a digital PLL with a 1-bit NCO. This allows the reference frequency f to be greater than the channel spacing, i. e. , the channel spacing can be smaller than the reference frequency f.

Digital Frequency Locked Loop And Phase Locked Loop Frequency Synthesizer

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US Patent:
7279988, Oct 9, 2007
Filed:
Mar 17, 2005
Appl. No.:
11/082277
Inventors:
Stephen T. Janesch - Greensboro NC, US
Eric J. King - Greensboro NC, US
Assignee:
RF Micro Devices, Inc. - Greensboro NC
International Classification:
H03L 7/00
US Classification:
331 10, 331 17
Abstract:
A frequency synthesizer including frequency and phase locked loop that operates in either a frequency locked loop (FLL) mode or a phase locked loop (PLL) mode. In a first state, the frequency and phase locked loop operates in the FLL mode for initial frequency acquisition. Once the frequency and phase locked loop has locked in FLL mode, the frequency and phase locked loop transitions to the PLL mode for normal operation.

Digitally Controlled Oscillator

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US Patent:
7336134, Feb 26, 2008
Filed:
Jun 25, 2004
Appl. No.:
10/877295
Inventors:
Stephen T. Janesch - Greensboro NC, US
Paul G. Martyniuk - Somerville MA, US
Assignee:
RF Micro Devices, Inc. - Greensboro NC
International Classification:
H03B 5/12
H03I 7/099
US Classification:
331 36C, 331117 R, 331 57, 331177 V, 331185
Abstract:
A tunable oscillator suitable for use in a frequency synthesizer of a transceiver is controlled by varying one or more parameters associated with the oscillator. In particular, a digital control signal affects one or more of the capacitances of the oscillator, the bias voltage of the oscillator, the supply voltage, or the bias current of the oscillator. Changes to one or more of these parameters allows the frequency of the oscillator to be controlled as desired.

Fractional-N Based Digital Afc System With A Translational Pll Transmitter

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US Patent:
7626462, Dec 1, 2009
Filed:
May 2, 2006
Appl. No.:
11/415578
Inventors:
Alexander Wayne Hietala - Phoenix AZ, US
Ryan Lee Bunch - Greensboro NC, US
Scott Robert Humphreys - Greensboro NC, US
Stephen T. Janesch - Greensboro NC, US
Assignee:
RF Micro Devices, Inc. - Greensboro NC
International Classification:
H03L 7/00
US Classification:
331 2
Abstract:
A fractional-N based Automatic Frequency Control (AFC) system for a mobile terminal is provided. In general, automatic frequency control is implemented in a frequency synthesizer to correct or compensate for a frequency error of an associated reference oscillator. The frequency synthesizer includes a first fractional-N phase-locked loop (FN-PLL) generating a baseband clock signal used by a baseband processor of the mobile terminal, a second FN-PLL generating a receiver local oscillator signal used by a receiver of the mobile terminal to downconvert a received radio frequency signal to a desired frequency, and a translational PLL generating a transmitter local oscillator signal used by a transmitter of the mobile terminal to provide a radio frequency transmit signal. The automatic frequency control is performed by applying a digital correction value, which is preferably multiplicative, to fractional-N dividers of the first and second FN-PLLs.
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Stephen T Janesch from Greensboro, NC, age ~62 Get Report