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Stephanie Ann Bojarski

from Beaverton, OR
Age ~35
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Also known as:
Stephanie A Bojarski
Phone and address:
10010 SW 135Th Ave, Beaverton, OR 97008
Related to:
Breanna Bojarski, 50Joseph F Bojarski, 70Patricia A Bojarski, 62Kevin John Bojarski, 33Stanley K BojarskiHelen BojarskiPaul M Bojarski, 64
Connected to:
Chelsea L Bojarski, 40Dagmara Bojarska, 45Ellen S Bojarski, 70Geraldine Bojarski, 64Karie E Bojarski, 49Phyllis M Bojarski, 91Sara Bojarski, 38Christopher F Bojarun, 53Edward J Bojas, 60Anna M Bojczuk, 70

Stephanie Bojarski Phones & Addresses

  • 10010 SW 135Th Ave, Beaverton, OR 97008
  • 1709 La Costa Ct, Pittsburgh, PA 15237 (412) 916-6463
  • Sherwood, OR

Work

Company: Cross link, cmu Oct 2013 Position: American ceramics society president's council of student advisors

Education

School / High School: Carnegie Mellon University- Pittsburgh, PA Aug 2010 Specialities: Ph.D. in Materials Science and Engineering

Resumes

Resumes

Stephanie Bojarski Photo 1

Stephanie Bojarski

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Location:
10010 southwest 135Th Ave, Beaverton, OR 97008
Industry:
Semiconductors
Work:
Carnegie Mellon University - Greater Pittsburgh Area since Aug 2010
Ph.D. Candidate
Plextronics Jun 2010 - Aug 2010
Device Engineering Intern
Lehigh University Aug 2009 - May 2010
Undergraduate Researcher
Stanford Nanofabrication Facility Jun 2009 - Aug 2009
NNIN REU Intern
Universal Stainless and Alloy Products Jun 2008 - Aug 2008
Metallurgy Intern
Education:
Carnegie Mellon University 2011 - 2014
Carnegie Mellon University 2010 - 2011
Lehigh University 2006 - 2010
Skills:
Afm
Materials Science
Microscopy
Tem
Scanning Electron Microscopy
Powder X Ray Diffraction
Matlab
Characterization
Experimentation
R&D
Nanotechnology
Ebsd
Sem
Data Analysis
Microsoft Office
Thin Films
Research
Xrd
Design of Experiments
Microstructure
Ceramics
Fortran
Collaboration
Event Planning
Multi Tasking
Awards:
Sandia National Lab. Graduate Research Fellowship
Claire and John Bertucci Fellowship in Engineering
Sapphire Award, Graduate Excellence in Materials Science (GEMS) Awards
MS&T 2012
Stephanie Bojarski Photo 2

Ph.d. Candidate At Carnegie Mellon University

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Position:
Ph.D. Candidate at Carnegie Mellon University
Location:
Greater Pittsburgh Area
Industry:
Research
Work:
Carnegie Mellon University - Greater Pittsburgh Area since Aug 2010
Ph.D. Candidate
Plextronics Jun 2010 - Aug 2010
Device Engineering Intern
Lehigh University Aug 2009 - May 2010
Undergraduate Researcher
Stanford Nanofabrication Facility Jun 2009 - Aug 2009
NNIN REU Intern
Universal Stainless and Alloy Products Jun 2008 - Aug 2008
Metallurgy Intern
Education:
Carnegie Mellon University 2011 - 2014
Carnegie Mellon University 2010 - 2011
Lehigh University 2006 - 2010
Skills:
Materials Science
Scanning Electron Microscopy
EBSD
AFM
SEM
TEM
XRD
Characterization
Ceramics
Microscopy
Matlab
Powder X-ray Diffraction
Awards:
Sandia National Lab. Graduate Research Fellowship
Claire and John Bertucci Fellowship in Engineering
Sapphire Award, Graduate Excellence in Materials Science (GEMS) Awards
MS&T 2012
Stephanie Bojarski Photo 3

Stephanie Bojarski Pittsburgh, PA

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Work:
Cross Link, CMU

Oct 2013 to 2000
American Ceramics Society President's Council of Student Advisors
Cross Link, CMU

Jan 2013 to 2000
Representative
Cross Link, CMU

Aug 2012 to 2000
Head of External Communications
Materials in Engineering

Sep 2011 to 2012
Plextronics
Pittsburgh, PA
Jun 2010 to Aug 2010
Internship
Undergraduate Research, Lehigh University

Aug 2009 to May 2010
Society of Women Engineers

Aug 2008 to May 2010
Treasurer
NNIN REU, Stanford University
Palo Alto, CA
Jun 2009 to Aug 2009
Lehigh Rowing Team, NCAA Division I

Aug 2006 to May 2009
Captain
Universal Stainless and Alloy Products
Pittsburgh, PA
Jun 2008 to Aug 2008
Internship
Education:
Carnegie Mellon University
Pittsburgh, PA
Aug 2010 to 2000
Ph.D. in Materials Science and Engineering
Carnegie Mellon University
Aug 2010 to 2000
RESEARCH
Carnegie Mellon University
Dec 2012
M.S. in character and energy
Lehigh University
Bethlehem, PA
May 2010
B.S. in Materials Science and Engineering

Publications

Us Patents

Leave-Behind Protective Layer Having Secondary Purpose

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US Patent:
20220246608, Aug 4, 2022
Filed:
Apr 21, 2022
Appl. No.:
17/726412
Inventors:
- Santa Clara CA, US
Anh PHAN - Beaverton OR, US
Ehren MANNEBACH - Tigard OR, US
Cheng-Ying HUANG - kPortland OR, US
Stephanie A. BOJARSKI - Beaverton OR, US
Gilbert DEWEY - Beaverton OR, US
Orb ACTON - Portland OR, US
Willy RACHMADY - Beaverton OR, US
International Classification:
H01L 27/088
H01L 29/423
H01L 29/08
H01L 21/762
H01L 23/528
H01L 29/78
H01L 29/06
Abstract:
Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

Lateral Gate Material Arrangements For Quantum Dot Devices

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US Patent:
20220190135, Jun 16, 2022
Filed:
Dec 10, 2020
Appl. No.:
17/117337
Inventors:
Roza Kotlyar - Portland OR, US
Stephanie A. Bojarski - Beaverton OR, US
Hubert C. George - Portland OR, US
Payam Amin - Portland OR, US
Patrick H. Keys - Portland OR, US
Ravi Pillarisetty - Portland OR, US
Roman Caudillo - Portland OR, US
Florian Luethi - Portland OR, US
James S. Clarke - Portland OR, US
International Classification:
H01L 29/49
H01L 29/06
H01L 29/423
H01L 29/15
G06N 10/00
Abstract:
Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

Integrated Quantum Circuit Assemblies For Cooling Apparatus

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US Patent:
20200403137, Dec 24, 2020
Filed:
Jun 24, 2019
Appl. No.:
16/450396
Inventors:
- Santa Clara CA, US
Ravi Pillarisetty - Portland OR, US
Nicole K. Thomas - Portland OR, US
Hubert C. George - Portland OR, US
Jeanette M. Roberts - North Plains OR, US
David J. Michalak - Portland OR, US
Roman Caudillo - Portland OR, US
Thomas Francis Watson - Portland OR, US
Stephanie A. Bojarski - Beaverton OR, US
James S. Clarke - Portland OR, US
International Classification:
H01L 39/02
H01L 39/04
H01L 39/22
H01L 23/46
H01L 23/552
H01L 27/18
G06N 10/00
Abstract:
Embodiments of the present disclosure describe integrated quantum circuit assemblies that include quantum circuit components pre-packaged, or integrated, with some other electronic components and mechanical attachment means for easy inclusion within a cooling apparatus. An example integrated quantum circuit assembly includes a package and mechanical attachment means for securing the package within a cryogenic chamber of a cooling apparatus. The package includes a plurality of components, such as a quantum circuit component, an attenuator, and a directional coupler, which are integral to the package. Such an integrated assembly may significantly speed up installation and may help develop systems for rapidly bringing up quantum computers.

Quantum Dot Devices With Multiple Layers Of Gate Metal

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US Patent:
20200312989, Oct 1, 2020
Filed:
Mar 26, 2019
Appl. No.:
16/365018
Inventors:
- Santa Clara CA, US
Sarah Atanasov - Beaverton OR, US
Ravi Pillarisetty - Portland OR, US
Lester Lampert - Portland OR, US
James S. Clarke - Portland OR, US
Nicole K. Thomas - Portland OR, US
Roman Caudillo - Portland OR, US
Kanwaljit Singh - Rotterdam, NL
David J. Michalak - Portland OR, US
Jeanette M. Roberts - North Plains OR, US
Stephanie A. Bojarski - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/775
H01L 29/423
H01L 29/78
H01L 29/66
G06N 10/00
Abstract:
Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.

Backside Contacts For Semiconductor Devices

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US Patent:
20200294998, Sep 17, 2020
Filed:
Mar 15, 2019
Appl. No.:
16/355195
Inventors:
- Santa Clara CA, US
EHREN MANNEBACH - Beaverton OR, US
ANH PHAN - Beaverton OR, US
RICHARD E. SCHENKER - Portland OR, US
STEPHANIE A. BOJARSKI - Beaverton OR, US
WILLY RACHMADY - Beaverton OR, US
PATRICK R. MORROW - Portland OR, US
JEFFERY D. BIELEFELD - Forest Grove OR, US
GILBERT DEWEY - Beaverton OR, US
HUI JAE YOO - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 27/088
H01L 29/78
H01L 29/06
H01L 21/8234
H01L 23/48
H01L 23/532
Abstract:
Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Non-Planar Transistors With Channel Regions Having Varying Widths

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US Patent:
20200295002, Sep 17, 2020
Filed:
Mar 15, 2019
Appl. No.:
16/354669
Inventors:
- Santa Clara CA, US
Leonard Guler - Hillsboro OR, US
Richard Schenker - Portland OR, US
Michael K. Harper - Hillsboro OR, US
Sam Sivakumar - Beaverton OR, US
Urusa Alaan - Hillsboro OR, US
Stephanie A. Bojarski - Beaverton OR, US
Achala Bhuwalka - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 27/092
H01L 29/78
H01L 29/10
H01L 29/06
H01L 29/423
H01L 29/786
H01L 29/16
H01L 29/20
H01L 21/02
H01L 21/306
H01L 21/3065
H01L 21/308
H01L 21/8252
H01L 21/8238
Abstract:
Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

Vertically Stacked Transistor Devices With Isolation Wall Structures Containing An Electrical Conductor

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US Patent:
20200273779, Aug 27, 2020
Filed:
Dec 27, 2017
Appl. No.:
16/646129
Inventors:
- Santa Clara CA, US
Anh PHAN - Beaveton OR, US
Patrick MORROW - Portland OR, US
Stephanie A. BOJARSKI - Beaverton OR, US
International Classification:
H01L 23/48
H01L 27/088
H01L 21/8234
Abstract:
An integrated circuit structure comprises a lower device layer that includes a first structure comprising a first set of transistor fins and a first set of contact metallization. An upper device layer is bonded onto the lower device layer, where the upper device layer includes a second structure comprising a second set of transistor fins and a second set of contact metallization. At least one power isolation wall extends from a top of the upper device layer to the bottom of the lower device layer, wherein the power isolation wall is filled with a conductive material such that power is routed between transistor devices on the upper device layer and the lower device layer.

Self-Aligned Local Interconnects

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US Patent:
20200258778, Aug 13, 2020
Filed:
Feb 13, 2019
Appl. No.:
16/274758
Inventors:
- Santa Clara CA, US
Ehren Mannebach - Beaverton OR, US
Anh Phan - Beaverton OR, US
Richard Schenker - Portland OR, US
Stephanie A. Bojarski - Beaverton OR, US
Willy Rachmady - Beaverton OR, US
Patrick Morrow - Portland OR, US
Jeffery Bielefeld - Forest Grove OR, US
Gilbert Dewey - Beaverton OR, US
Hui Jae Yoo - Hillsboro OR, US
Nafees Kabir - Portland OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 21/768
H01L 29/78
H01L 29/66
H01L 27/092
H01L 23/522
H01L 21/02
H01L 21/8238
Abstract:
In some embodiments, a semiconductor device structure is formed by using an angled etch to remove material so as to expose a portion of an adjacent conductor. The space formed upon removing the material can then be filled with a conductive material during formation of a contact or other conductive structure (e.g., and interconnection). In this way, the contact formation also fills the space to form an angled local interconnect portion that connects adjacent structures (e.g., a source/drain contact to an adjacent source/drain contact, a source/drain contact to an adjacent gate contact, a source/drain contact to an adjacent device level conductor also connected to a gate/source/drain contact). In other embodiments, an interconnection structure herein termed a “jogged via” establishes and electrical connection from laterally adjacent peripheral surfaces of conductive structures that are not coaxially or concentrically aligned with one another.
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Stephanie Ann Bojarski from Beaverton, OR, age ~35 Get Report