Steffen A Loeffler

6373286, Apr 16, 2002

Jun 26, 2000

09/603631

Steffen Loeffler - Essex Junction VT
Peter Poechmueller - Munich, DE

Siemens Aktiengesellschaft - Munich
International Business Machines Corporation - Armonk NY

H03K 19094

326 86, 326 17, 326 27, 326 83, 326102

An array of multiple off chip drivers on an integrated circuit (IC) chip has reduced synchronous switching output timing error (TSSO) at high speeds of operation. The array includes a pair of low resistance buses to provide charge and discharge paths for the outputs, a plurality of terminals connecting the respective drivers between the buses, the resistance of each terminal being substantially greater than the resistance of either bus, and a plurality of capacitors connected internally of the respective drivers. Each driver has an input for receiving binary data from a memory unit and an output terminal which is switched in accordance with the binary input data to a higher or lower voltage level. There are a plurality of transistor switches within each driver which selectively couple a capacitor to the output terminal when it is driven high and at the same time couple another capacitor to one of the buses, and vice versa when the output terminal is driven low.

7737750, Jun 15, 2010

Jan 16, 2007

11/653312

Steffen Loeffler - Essex VT, US

Infineon Technologies AG - Neubiberg

H03L 7/06

327279, 327160, 327265

A trimming system for determining a trim solution for a semiconductor device includes an internal value generating circuit for generating an internal value based upon a counter value. The relationship between the internal delay value and an external reference is compared to determine if the counter value is a possible trim solution, while predetermined counter values are excluded as a trim solution.

7855929, Dec 21, 2010

Sep 26, 2008

12/239624

Jochen Hoffmann - Colchester VT, US
Steffen Loeffler - Cary NC, US

Qimonda AG - Munich

G11C 7/00

365222, 365226

Embodiments of the invention generally related to arrangements of decoupling capacitor arrays in an integrated circuit. A decoupling capacitor array may include a plurality of bit lines that are electrically coupled to each other, a plurality of word lines that are electrically coupled to each other, and a plurality of decoupling capacitors, each decoupling capacitor coupled to a respective bit line and word line. The decoupling capacitor array may further include an access circuit electrically coupled to the plurality of word lines and a power grid, the access circuit being configured to either connect or disconnect the decoupling capacitor array to the power grid based on a control signal.

7889589, Feb 15, 2011

Mar 24, 2008

12/053913

Steffen Loeffler - Essex Junction VT, US
Wolfgang Hokenmaier - Burlington VT, US

Qimonda AG - München

G11C 8/00

36523003, 36518511, 36523005

A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells.

7894283, Feb 22, 2011

Aug 8, 2008

12/188558

Margaret Freebern - Richmond VT, US
Wolfgang Hokenmaier - Lausanne, CH
Donald Labrecque - Colchester VT, US
Steffen Loeffler - Cary NC, US
Ralf Klein - Deidesheim, DE

Qimonda AG - München

G11C 11/00

365201, 36518905

An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array.

7969807, Jun 28, 2011

Mar 5, 2008

12/042785

Wolfgang Hokenmaier - Burlington VT, US
Farrukh Aquil - Essex Junction VT, US
Steffen Loeffler - Essex Junction VT, US

Qimonda AG - Munich

G11C 7/00

365222, 365195, 365196, 36523003, 36523006, 36523008

A memory including an array of memory cells and a control circuit. The control circuit is configured to control partial array self refreshes and to switch from one partial array self refresh to another partial array self refresh. Data in memory cells that are refreshed via the one partial array self refresh and refreshed via the other partial array self refresh is retained in the memory cells from before a first switch from the one partial array self refresh to the other partial array self refresh to after the first switch.

20080266990, Oct 30, 2008

Apr 30, 2007

11/790934

Steffen Loeffler - Essex Junction VT, US

Infineon Technologies North America Corp. - San Jose CA

G11C 7/00

365201

A redundancy replacement scheme for repairing a faulty memory cell including memory cells arranged in memory blocks containing word lines and column select lines. The redundancy replacement scheme including replacing the faulty memory cell in a second memory block with a spare memory cell in the second memory block based on a decoded address of a first memory block.

20100079150, Apr 1, 2010

Sep 26, 2008

12/239575

Jochen Hoffmann - Colchester VT, US
Steffen Loeffler - Cary NC, US

G01R 31/12
G01R 31/02

324548, 324550

Embodiments of the invention generally provide methods, systems, and apparatus for testing decoupling capacitors of an integrated circuit. A decoupling capacitor may be disconnected from the power grid of the integrated circuit during testing. The voltage of the decoupling capacitor may be compared to the voltage of a reference capacitor to determine whether the decoupling capacitor is defective. If the decoupling capacitor is determined to be defective, the decoupling capacitor is not reconnected to the power grid, thereby reducing the leakage currents in the integrated circuit.