Stefanos Kaxiras

6658551, Dec 2, 2003

Mar 30, 2000

09/538757

Alan David Berenbaum - New York City NY
Nevin Heintze - Morristown NJ
Tor E. Jeremiassen - Somerset NJ
Stefanos Kaxiras - Jersey City NJ

Agere Systems Inc. - Allentown PA

G06F 900

712 24, 712215, 717161

A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word (VLIW) architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. There are times, however, when instruction packets cannot be split without violating the semantics of the instruction packet assembled by the compiler. A packet split identification bit is disclosed that allows hardware to efficiently determine when it is permissible to split an instruction packet. The split bit informs the hardware when splitting is prohibited.

6665791, Dec 16, 2003

Mar 30, 2000

09/538669

Alan David Berenbaum - New York City NY
Nevin Heintze - Morristown NJ
Tor E. Jeremiassen - Somerset NJ
Stefanos Kaxiras - Jersey City NJ

Agere Systems Inc. - Allentown PA

G06F 15163

712 24, 712231, 709102, 709104, 709106

A method and apparatus are disclosed for releasing functional units in a multithreaded very large instruction word (VLIW) processor. The functional unit release mechanism can retrieve the capacity lost due to multiple cycle instructions. The functional unit release mechanism of the present invention permits idle functional units to be reallocated to other threads, thereby improving workload efficiency. Instruction packets are assigned to functional units, which can maintain their state, independent of the issue logic. Each functional unit has an associated state machine (SM) that keeps track of the number of cycles that the functional unit will be occupied by a multiple-cycle instruction. Functional units do not reassign themselves as long as the functional unit is busy. When the instruction is complete, the functional unit can participate in functional unit allocation, even if other functional units assigned to the same thread are still busy. The functional unit release approach of the present invention allows the functional units that are not associated with a multiple-cycle instruction to be allocated to other threads while the blocked thread is waiting, thereby improving throughput of the multithreaded VLIW processor.

6889293, May 3, 2005

Jun 9, 2000

09/591918

Stefanos Kaxiras - Jersey City NJ, US
Reginald Clifford Young - New York NY, US

Agere Systems Inc. - Allentown PA

G06F012/00

711147, 711119, 711124, 709213

A set of predicted readers are determined for a data block subject to a write request in a shared-memory multiprocessor system by first determining a current set of readers of the data block, and then generating the set of predicted readers based on the current set of readers and at least one additional set of readers representative of at least a portion of a global history of a directory associated with the data block. In one possible implementation, the set of predicted readers are generated by applying a function to the current set of readers and one or more additional sets of readers.

6983388, Jan 3, 2006

May 25, 2001

09/865847

Stefanos Kaxiras - Jersey City NJ, US
Philip W. Diodato - Asbury NJ, US
Girija Narlikar - Jersey City NJ, US

Agere Systems Inc. - Allentown PA

G06F 1/32

713324, 713320, 711145

A method and apparatus are disclosed for reducing leakage power in a cache memory. A cache decay technique is employed for both data and instruction caches that removes power from cache lines that have not been accessed for a predefined time interval, referred to as the decay interval. The cache-line granularity of the present invention permits a significant reduction in leakage power while at the same time preserving much of the performance of the cache. The decay interval is maintained using a timer that is reset each time the corresponding cache line is accessed. The decay interval may be fixed or variable. Once the decay interval timer exceeds a specified decay interval, power to the cache line is removed. Once power to the cache line is removed, the contents of the data and tag fields are allowed to decay and the valid bit associated with the cache line is reset. When a cache line is later accessed after being powered down by the present invention, a cache miss is incurred while the cache line is again powered up and the data is obtained from the next level of the memory hierarchy.

7007153, Feb 28, 2006

Mar 30, 2000

09/538670

Alan David Berenbaum - New York City NY, US
Nevin Heintze - Morristown NJ, US
Tor E. Jeremiassen - Somerset NJ, US
Stefanos Kaxiras - Jersey City NJ, US

Agere Systems Inc. - Allentown PA

G06F 15/00
G06F 15/76

712 24, 718103, 718107

A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional VLIW architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes a compiler to detect parallelism. The disclosed multithreaded VLIW architecture exploits program parallelism by issuing multiple instructions, in a similar manner to single threaded VLIW processors, from a single program sequencer, and also supports multiple program sequencers, as in simultaneous multithreading. Instructions are allocated to functional units to issue multiple VLIW instructions to multiple functional units in the same cycle. The allocation mechanism of the present invention occupies a pipeline stage just before arguments are dispatched to functional units. The allocate stage determines how to group the instructions together to maximize efficiency, by selecting appropriate instructions and assigning the instructions to the FUs.

7096343, Aug 22, 2006

Mar 30, 2000

09/538755

Alan David Berenbaum - New York City NY, US
Nevin Heintze - Morristown NJ, US
Tor E. Jeremiassen - Somerset NJ, US
Stefanos Kaxiras - Jersey City NJ, US

Agere Systems Inc. - Allentown PA

G06F 9/50

712 24, 712231, 712215, 718102, 718104, 718106

A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very long instruction word architectures and conventional multithreaded architectures to reduce execution time within an individual program, as well as across a workload. The present invention utilizes instruction packet splitting to recover some efficiency lost with conventional multithreaded architectures. Instruction packet splitting allows an instruction bundle to be partially issued in one cycle, with the remainder of the bundle issued during a subsequent cycle. The allocation hardware assigns as many instructions from each packet as will fit on the available functional units, rather than allocating all instructions in an instruction packet at one time. Those instructions that cannot be allocated to a functional unit are retained in a ready-to-run register. On subsequent cycles, instruction packets in which all instructions have been issued to functional units are updated from their thread's instruction stream, while instruction packets with instructions that have been held are retained.

20030145241, Jul 31, 2003

Jan 30, 2002

10/060661

Zhigang Hu - Princeton NJ, US
Stefanos Kaxiras - Jersey City NJ, US
Margaret Martonosi - Skillman NJ, US

G06F001/26

713/320000

An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.

20060041769, Feb 23, 2006

Oct 7, 2005

11/245513

Zhigang Hu - Princeton NJ, US
Stefanos Kaxiras - Jersey City NJ, US
Margaret Martonosi - Skillman NJ, US

G06F 1/30

713324000

An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.