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Stanley R Szerlip

from Longmont, CO
Deceased

Stanley Szerlip Phones & Addresses

  • 7475 Mount Sherman Rd, Longmont, CO 80503 (303) 530-3228
  • Las Vegas, NV
  • Sandy, UT
  • Park City, UT
  • 7475 Mount Sherman Rd, Longmont, CO 80503 (303) 907-0438

Work

Company: Stanley szerlip artwork 2013 to 2015 Position: Stanley szerlip artwork

Education

Degree: High school graduate or higher

Industries

Design

Resumes

Resumes

Stanley Szerlip Photo 1

Stanley Szerlip

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Industry:
Design
Work:
Stanley Szerlip Artwork 2013 - 2015
Stanley Szerlip Artwork

Business Records

Name / Title
Company / Classification
Phones & Addresses
Stanley Szerlip
Professional Engineer
Mentor Graphics Corp
Muralist · Custom Computer Programming Services · Computer Integrated Systems Design · Electronic Computer Mfg
1811 Pike Rd STE 2F, Longmont, CO 80501
(303) 770-2656, (949) 737-4567, (720) 494-1000, (720) 494-1054

Publications

Us Patents

Thermally Conductive Elastomeric Interposer Connection System

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US Patent:
52734390, Dec 28, 1993
Filed:
Mar 11, 1993
Appl. No.:
8/029825
Inventors:
Stanley R. Szerlip - Longmont CO
Floyd G. Paurus - Boulder CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
H01R 909
H01R 13533
US Classification:
439 66
Abstract:
A multi-chip module electrical and thermal conducting apparatus is provided. The apparatus is disposed between layers or boards of the module and includes electrical conducting traces. Electrical conductors are deposited on the faces of the layers and the traces electrically interconnect the electrical conductors of the two layers. The traces are joined to an elastomeric body and insulating material that are essentially non-conductive of electrical and thermal energy. The apparatus includes a thermal conduction unit that acts as a thermal shunt around the body and insulating material. The thermal conduction unit is electrically isolated from the traces. Thermal energy is received by the thermal conduction unit when heat is generated by the activation of electronic components mounted on the module layers. The thermal energy received by the thermal conduction unit is carried away by thermal vias formed in the module layers.

Printed Circuit Board Having An Integrated Decoupling Capacitive Element

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US Patent:
51629771, Nov 10, 1992
Filed:
Aug 27, 1991
Appl. No.:
7/750409
Inventors:
Floyd G. Paurus - Boulder CO
Archibald W. Smith - Boulder CO
Stanley R. Szerlip - Longmont CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
H05K 103
H05K 118
B32B 900
US Classification:
361401
Abstract:
A printed circuit board is disclosed which includes a high capacitance power distribution core, the manufacture of which is compatible with standard printed circuit board assembly technology. The high capacitance core consists of a ground plane and a power plane separated by a planar element having a high dielectric constant. The high dielectric constant material is typically glass fiber impregnated with a bonding material, such as epoxy resin loaded with a ferro-electric ceramic substance having a high dielectric constant. The ferro-electric ceramic substance is typically a nanopowder combined with an epoxy bonding material. The resulting capacitance of the power distribution core is typically sufficient to totally eliminate the need for decoupling capacitors on a typical printed circuit board.

Memory Stack With An Integrated Interconnect And Mounting Structure

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US Patent:
54485118, Sep 5, 1995
Filed:
Jun 1, 1994
Appl. No.:
8/252609
Inventors:
Floyd G. Paurus - Boulder CO
Stanley R. Szerlip - Longmont CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
G11C 504
G06K 1907
US Classification:
365 52
Abstract:
A memory stack includes a flexible interconnect device having a plurality of rigid sections connected together by a plurality of flexible sections. Memory devices such as dice or chips are mounted on the flexible interconnect structure and the structure is folded to at the flexible sections to form a stack. Connections among memory device I/Os and interconnect device mounting contacts are made via traces in a signal layer. A thermal conduction layer can be added to increase heat conduction away from the memory devices.

Printed Circuit Board Having Integrated Decoupling Capacitive Core With Discrete Elements

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US Patent:
54284996, Jun 27, 1995
Filed:
Jan 28, 1993
Appl. No.:
8/010129
Inventors:
Stanley R. Szerlip - Longmont CO
Floyd G. Paurus - Boulder CO
Archibald W. Smith - Boulder CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
H01G 438
US Classification:
361328
Abstract:
A printed circuit board laminate is disclosed having a high capacitance power distribution core. The power distribution core comprises a pair of conductive plates electrically connected to an array of high capacitance core tiles, separated by a compliant dielectric filler. The resulting capacitance of the power distribution core is sufficient to eliminate the need for decoupling capacitors on a typical printed circuit board. Separate power supply areas of variable decoupling capacitance can be formed for mounted integrated circuits with different power supply requirements. A method for manufacturing such board laminates is also disclosed that is compatible with standard printed circuit board assembly technology.

Method Of Fabricating A Printed Circuit Board Power Core Using Powdered Ceramic Materials In Organic Binders

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US Patent:
55049931, Apr 9, 1996
Filed:
Aug 30, 1994
Appl. No.:
8/297799
Inventors:
Stanley R. Szerlip - Longmont CO
Floyd G. Paurus - Boulder CO
Frances Planinsek - Louisville CO
Robert D. Stroud - Boulder CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
H05K 310
H05K 103
US Classification:
29849
Abstract:
A method of fabricating a printed circuit board power core is disclosed wherein ceramic particles that have a diameter that is approximately equal to the desired dielectric thickness are combined with dielectric powders that have a relatively very small size. To produce a dielectric core using this technique, a dielectric material mixture is applied between two conductor layers and bonded therebetween. This dielectric material mixture preferably has a concentration of large particles equal to the desired core thickness with a loading factor of large/small particles less than the maximum ratio needed to provide the desired dielectric constant, but greater than the ratio required to provide stability during the pressing and curing steps.

Integrated Decoupling Capacitive Core For A Printed Circuit Board And Method Of Making Same

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US Patent:
54693241, Nov 21, 1995
Filed:
Oct 7, 1994
Appl. No.:
8/319651
Inventors:
Watson R. Henderson - Broomfield CO
Floyd G. Paurus - Boulder CO
Stanley R. Szerlip - Longmont CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
H01G 4018
US Classification:
3613012
Abstract:
A printed circuit board includes a planar first outer layer, a planar second outer layer, and a planar capacitive power distribution core disposed between the first and second outer layers. The capacitive core is formed from first and second electrically conductive layers with a dielectric layer disposed therebetween. The dielectric layer is made from a high dielectric constant material such as a ceramic in the form of a perforated sheet. The perforations permit the electrically conductive layers to be bound to the dielectric layer without significantly increasing the separation between the conductive layers. Each perforation allows a column of adhesive to collect therein to bond the power distribution core together. The resulting capacitance is typically sufficient to eliminate the need for decoupling capacitors.

Solid State Memory Device Having Optical Data Connections

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US Patent:
52745848, Dec 28, 1993
Filed:
May 6, 1991
Appl. No.:
7/696357
Inventors:
Watson R. Henderson - Broomfield CO
Michael S. Kelly - Westminster CO
Michael L. Leonhardt - Longmont CO
Floyd G. Paurus - Boulder CO
Archibald W. Smith - Boulder CO
Stanley R. Szerlip - Longmont CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
G11C 506
US Classification:
365 64
Abstract:
The solid state memory device consists of a circuit board based system which is mounted in a 3480 type magnetic tape cartridge form factor housing to make this media physically compatible with the 3480 type magnetic tape cartridges. The interconnection of the solid state memory device with the read/write device is by an optical connections which transfer data between the solid state memory device and the associated read/write device. A plurality of batteries in the solid state memory device provide power for the memory retention capability required of the volatile solid state memory devices. The batteries are recharged by the use of a pair of power rails that are incorporated into the exterior housing of the 3480 form factor cartridge. Thus, the associated read/write device applies power to the solid state memory via these power rails when the 3480 form factor cartridge is placed in the associated read/write device. Likewise, an associated manual or automated cartridge storage system supplies power when the cartridge is offline, in storage.
Stanley R Szerlip from Longmont, CODeceased Get Report