Srinivasa Babu Gopaladhine

6549926, Apr 15, 2003

Oct 26, 1999

09/427366

Atul Kalambur - Palo Alto CA
Srinivasa Gopaladhine - San Jose CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 752

708650

A Sweeney, Robertson, Tocher (SRT) divider for use in a computer system has recoding circuitry to recode the three most significant bits of the dividend into one-hot form as the dividend is loaded into a quotient/partial remainder register. With each clock, a partial remainder is generated also having its most significant three bits in one-hot form and the remaining bits in binary encoded form. The divider has several stages permitting it to generate several bits of quotient in each clock cycle. Each stage has circuitry for estimating a quotient digit, and for computing a partial remainder by subtracting the product of the quotient digit times the divisor from either the dividend or a previous partial remainder. This subtraction is performed upon a one-hot code in the most significant bits and in binary code on the least significant bits. The divider also has circuitry for assembling a plurality of quotient digits into a quotient.

6466497, Oct 15, 2002

Apr 17, 2001

09/838774

Shaishav A. Desai - San Jose CA
Anup S. Mehta - Fremont CA
Srinivasa Gopaladhine - San Jose CA

Sun Microsystems, Inc. - Palo Alto CA

G11C 700

365203, 365204, 365202, 36518907

An electronic circuit has a register connected to a sense amplifier via a bitline (the sense amplifier has a primary precharge circuit), and a secondary precharge circuit also connected to the bitline. For bitlines that are relatively long, the secondary precharge circuit is located at a distal end of the bitline with respect to the sense amplifier. The secondary precharge circuit initially pulls up the voltage of the bitline, and the primary precharge circuit in the sense amplifier completes the precharging of the bitline. The secondary precharge circuit includes a cascode transistor coupled to the bitline via a feedback circuit. The feedback circuit is enabled during the precharge phase, when the bitline is discharged below a preset threshold. The threshold of the secondary precharge circuit can be set such that any skew between the precharge pulses of the secondary precharge circuit and the sense amplifier does not affect the falling bitline during the sense amplifier evaluate phase. Because of the initial surge of precharge from the secondary precharge circuit, the bitline is completely precharged in a shorter cycle time, allowing the sense amplifier to be operated at higher frequencies.