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Sivakumar P Mudanai

from Lake Oswego, OR
Age ~49
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Also known as:
Sivakumar R Mudanai, Sivakumar Mudani, Sivakumar Mudana, Mudanai Sivakumar, Sivakumar L
Phone and address:
17018 Summer Pl, West Linn, OR 97035
(503) 648-6337
Related to:
Anjum S Mukadam, 50Shabana Insaf, 57
Connected to:
Marian J Mudar, 74Muhammad Mudassar, 53Syed M Mudassar, 59Ahmed Mudasser, 37Catherine K Mudavadi, 65Hani Mudawar, 40Lenore S Muday, 86Anne F Mudd, 37Benjamin Mudd, 37Bethany A Mudd, 43

Sivakumar Mudanai Phones & Addresses

  • 17018 Summer Pl, Lake Oswego, OR 97035 (503) 648-6337
  • 662 NE Valarie Ct, Hillsboro, OR 97124 (503) 648-6337
  • Beaverton, OR
  • Republic, MO
  • Rogersville, MO
  • 2502 Leon St, Austin, TX 78705
  • 11028 Jollyville Rd, Austin, TX 78759
  • Greenview, MO

Publications

Us Patents

Junctionless Accumulation-Mode Devices On Prominent Architectures, And Methods Of Making Same

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US Patent:
8507948, Aug 13, 2013
Filed:
Dec 23, 2010
Appl. No.:
12/978248
Inventors:
Annalisa Cappellani - Portland OR, US
Kelin J. Kuhn - Aloha OR, US
Rafael Rios - Portland OR, US
Titash Rakshit - Hillsboro OR, US
Sivakumar P. Mudanai - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 29/66
US Classification:
257192, 257347, 257288, 257E29242, 257E21409, 257E21158, 438197, 438478, 438157, 438270
Abstract:
A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

Method Of Fabricating A Mosfet Transistor Having An Anti-Halo For Modifying Narrow Width Device Performance

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US Patent:
20070145495, Jun 28, 2007
Filed:
Dec 27, 2005
Appl. No.:
11/319815
Inventors:
Giuseppe Curello - Portland OR, US
Sivakumar Mudanai - Hillsboro OR, US
Nick Lindert - Beaverton OR, US
Leonard Pipes - Beaverton OR, US
M. Shaheed - Beaverton OR, US
Sunit Tyagi - Portland OR, US
International Classification:
H01L 29/78
H01L 21/336
US Classification:
257402000, 438289000, 438296000
Abstract:
A method including forming a transistor structure structure comprising a gate electrode over an active region of a substrate, the active region defined by a trench isolation structure and changing a performance of a narrow width transistor with respect to a wide width transistor by introducing a dopant into the active region adjacent an interface defined by the trench isolation structure and the gate electrode. A structure including a gate electrode formed on a substrate, an active region adjacent an interface defined by a trench isolation structure and a gate electrode and an implant within the active region to change a performance of a transistor.

Time-Domain Device Noise Simulator

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US Patent:
20070233444, Oct 4, 2007
Filed:
Mar 31, 2006
Appl. No.:
11/395537
Inventors:
Frank O'Mahony - Portland OR, US
Haydar Kutuk - Portland OR, US
Bryan Casper - Hillsboro OR, US
Eyal Fayneh - Givatayim, IL
Sivakumar Mudanai - Hillsboro OR, US
Wei-kai Shih - Sunnyvale CA, US
Farag Fattouh - Folsom CA, US
International Classification:
G06F 17/50
US Classification:
703014000
Abstract:
In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.

Junctionless Accumulation-Mode Devices On Decoupled Prominent Architectures

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US Patent:
20130334572, Dec 19, 2013
Filed:
Aug 12, 2013
Appl. No.:
13/964696
Inventors:
Annalisa Cappellani - Portland OR, US
Kelin J. Kuhn - Aloha OR, US
Rafael Rios - Portland OR, US
Titash Rakshit - Hillsboro OR, US
Sivakumar Mudanai - Hillsboro OR, US
International Classification:
H01L 29/205
H01L 29/78
US Classification:
257192, 257347
Abstract:
A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconducive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.

Junctionless Accumulation-Mode Device Isolated From Semiconductive Substrate By Reverse-Bias Junction

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US Patent:
20150021553, Jan 22, 2015
Filed:
Oct 6, 2014
Appl. No.:
14/507044
Inventors:
- Santa Clara CA, US
KELIN J. KUHN - Aloha OR, US
RAFAEL RIOS - Portland OR, US
Titash Rakshit - Hillsboro OR, US
Sivakumar Mudanai - Hillsboro OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 29/775
H01L 29/66
H01L 29/06
US Classification:
257 29, 438299
Abstract:
A junctionless accumulation-mode (JAM) semiconductive device is isolated from a semiconductive substrate by a reverse-bias band below a prominent feature of a JAM semiconductive body. Processes of making the JAM device include implantation and epitaxy.
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Sivakumar P Mudanai from Lake Oswego, OR, age ~49 Get Report